Datasheet HMC983LP5E (Analog Devices) - 5
| 制造商 | Analog Devices |
| 描述 | DC - 7 GHz Fractional-N Divider and Frequency Sweeper |
| 页数 / 页 | 32 / 5 — HMC983LP5E. DC - 7 GHz FRACTIONAL-N DIVIDER. AND FREQUENCY SWEEPER. … |
| 文件格式/大小 | PDF / 1.9 Mb |
| 文件语言 | 英语 |
HMC983LP5E. DC - 7 GHz FRACTIONAL-N DIVIDER. AND FREQUENCY SWEEPER. Figure 13. 100 MHz Output Swing vs Buffer Current
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HMC983LP5E
v02.0112
DC - 7 GHz FRACTIONAL-N DIVIDER AND FREQUENCY SWEEPER Figure 13. 100 MHz Output Swing vs Buffer Current
[7]
Figure 14. Input Return Loss
0.9 0 t pp) 0.85 M ING (V 0.8 -5 ) s W B 0.75 (d UT S S S O 0.7 -10 s - D OUTP 0.65 TURN L r NDE RE -E -40 C -15 o E 0.6 +27 C t INGL S 0.55 +85 C c 0.5 -20 e 12 13 14 15 16 17 18 0 2000 4000 6000 8000 t OUTPUT BUFFER CURRENT (mA) FREQUENCY (MHz) e
Figure 15. Two Way Frequency Sweep, Figure 16. One Way Frequency Sweep, 50 MHz PFD
[8]
10 MHz PFD and 10 Hz external trigger
[8] s & D 7000 7000 r 6900 6900 e ) iD 6800 6800 Hz Hz (M (M iv 6700 6700 NCY NCY UE UE Q Q 6600 6600 RE RE F y D F c 6500 6500 n 6400 6400 e 0 5 10 15 20 0 200 400 600 800 1000 TIME (ms) TIME (ms) u q e
Figure 17. PLL Cycle Slip Prevention, Figure 18. PLL Cycle Slip Prevention,
r
100 MHz PFD
[8]
50 MHz PFD
[8] F 7050 7050 CSP Enabled ) 7000 Reg0Eh[18:15] = 1h 7000 CSP Enabled Hz Reg0Eh[18:15] = Fh (M CSP Enabled (GHz) 6950 Reg0Eh[18:15] = 8h 6950 CSP Enabled NCY NCY Reg0Eh[18:15] = 5h UE 6900 UE Q Q 6900 RE F 6850 Cycle Slip Disabled 6850 UT UT FRE Cycle Slip Disabled P UT 6800 O 6800 L L LL OUTP P 6750 P 6750 6700 6700 0 50 100 150 200 250 300 0 50 100 150 200 250 300 TIME (us) TIME (us) [6] Measured with 50 Ω impedance per line. Buffer current is controled via reg 0Fh[4:2]. [7] Measured with 50 Ω impedance per line. Buffer current is controled via reg 0Fh[4:2]. [8] Measured with HMc983LP5e/HMc984LP4e chip set as fractional-n synthesizer. crystal input frequency = 100 MHz, cP current = 2.5 mA, cP offset current = 245 uA, Loop filter bandwidth = 87 KHz, DsM Mode B selected. cycle slip Prevention (csP) is disabled in HMc984LP4e by setting reg 01h [4] = 0. setting reg 01h [4] = 1 enables csP in the two chip PLL. Inf F or o m r p atio r n ifc ur e n , d ishe e d lbiv y e A r n y a alog n D d t evic o p es is la beclie o eved rd to ebre sa: H ccur iattti e tae M nd re ilicarbloew . H a o ve C wever, o n rp o For price, delivery, and to place orders: Analog Devices, Inc., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other oration, 2 Elizabeth Drive, Chelmsford, MA 01824 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 Phone: 978-250-3343 Fax: 978-250-3373 O rights of third parties that may result from its use. Specifications subject to change without notice. No P rd ho e ne r O : 7 n 81- -3li 2n 9 e a -47 t w 0 w 0 • O w rd .h e it r o tniltie n .c e ao t m
5
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. www.analog.com Application Support: Pho Trademarks and registered trademarks are the property of their respective owners. ne: 978-250-33 A 4 p 3 o plica r a tio p n S p u s p @ po h rt itt : P ite ho . n c e o : 1m -800-ANALOG-D
v02.0112
DC - 7 GHz FRACTIONAL-N DIVIDER AND FREQUENCY SWEEPER Figure 13. 100 MHz Output Swing vs Buffer Current
[7]
Figure 14. Input Return Loss
0.9 0 t pp) 0.85 M ING (V 0.8 -5 ) s W B 0.75 (d UT S S S O 0.7 -10 s - D OUTP 0.65 TURN L r NDE RE -E -40 C -15 o E 0.6 +27 C t INGL S 0.55 +85 C c 0.5 -20 e 12 13 14 15 16 17 18 0 2000 4000 6000 8000 t OUTPUT BUFFER CURRENT (mA) FREQUENCY (MHz) e
Figure 15. Two Way Frequency Sweep, Figure 16. One Way Frequency Sweep, 50 MHz PFD
[8]
10 MHz PFD and 10 Hz external trigger
[8] s & D 7000 7000 r 6900 6900 e ) iD 6800 6800 Hz Hz (M (M iv 6700 6700 NCY NCY UE UE Q Q 6600 6600 RE RE F y D F c 6500 6500 n 6400 6400 e 0 5 10 15 20 0 200 400 600 800 1000 TIME (ms) TIME (ms) u q e
Figure 17. PLL Cycle Slip Prevention, Figure 18. PLL Cycle Slip Prevention,
r
100 MHz PFD
[8]
50 MHz PFD
[8] F 7050 7050 CSP Enabled ) 7000 Reg0Eh[18:15] = 1h 7000 CSP Enabled Hz Reg0Eh[18:15] = Fh (M CSP Enabled (GHz) 6950 Reg0Eh[18:15] = 8h 6950 CSP Enabled NCY NCY Reg0Eh[18:15] = 5h UE 6900 UE Q Q 6900 RE F 6850 Cycle Slip Disabled 6850 UT UT FRE Cycle Slip Disabled P UT 6800 O 6800 L L LL OUTP P 6750 P 6750 6700 6700 0 50 100 150 200 250 300 0 50 100 150 200 250 300 TIME (us) TIME (us) [6] Measured with 50 Ω impedance per line. Buffer current is controled via reg 0Fh[4:2]. [7] Measured with 50 Ω impedance per line. Buffer current is controled via reg 0Fh[4:2]. [8] Measured with HMc983LP5e/HMc984LP4e chip set as fractional-n synthesizer. crystal input frequency = 100 MHz, cP current = 2.5 mA, cP offset current = 245 uA, Loop filter bandwidth = 87 KHz, DsM Mode B selected. cycle slip Prevention (csP) is disabled in HMc984LP4e by setting reg 01h [4] = 0. setting reg 01h [4] = 1 enables csP in the two chip PLL. Inf F or o m r p atio r n ifc ur e n , d ishe e d lbiv y e A r n y a alog n D d t evic o p es is la beclie o eved rd to ebre sa: H ccur iattti e tae M nd re ilicarbloew . H a o ve C wever, o n rp o For price, delivery, and to place orders: Analog Devices, Inc., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other oration, 2 Elizabeth Drive, Chelmsford, MA 01824 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 Phone: 978-250-3343 Fax: 978-250-3373 O rights of third parties that may result from its use. Specifications subject to change without notice. No P rd ho e ne r O : 7 n 81- -3li 2n 9 e a -47 t w 0 w 0 • O w rd .h e it r o tniltie n .c e ao t m
5
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. www.analog.com Application Support: Pho Trademarks and registered trademarks are the property of their respective owners. ne: 978-250-33 A 4 p 3 o plica r a tio p n S p u s p @ po h rt itt : P ite ho . n c e o : 1m -800-ANALOG-D