Datasheet AD74412R (Analog Devices) - 4

AD74412R Data Sheet FUNCTIONAL BLOCK DIAGRAM REFOUT REFIN ALDO1V8 ALDO5V AVDD AD74412R 2.5V 1.8V 5V VREF ALDO LDO IOVDD DVCC CCOMP_x1 DLDO1V8 1.8V INTERNAL DAC VIOUTP_x1 DLDO OSCILLATOR CASCODE_x1 DGND OUTPUT/ VIOUTN_x1 SCLK INPUT SYNC CONFIGURE SENSEH_x1 SDI 16-BIT SENSEHF_x1 ADC SDO SENSEL_x1 INPUT ALERT SHIFT SENSELF_x1 REGISTER ADC_RDY AND DIGITAL LDAC DIAGNOSTICS LOGIC CHANNELS GPO_A UX M GPO_B GPO_C THRESHOLD GPO_D CHANNEL A POWER-ON CHANNEL B RESET RESET CHANNEL C AVSS = –DVCC CHARGE PUMP CHANNEL D AGND1 AVSS CPUMP_N CPUMP_P AGND2 AGND3 AGND_SENSE
001
1x = A, B, C, AND D
21274- Figure 1. Rev. A | Page 4 of 66 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION COMPANION PRODUCTS PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS VOLTAGE OUTPUT CURRENT OUTPUT VOLTAGE INPUT CURRENT INPUT EXTERNALLY POWERED CURRENT INPUT LOOP POWERED RTD MEASUREMENT DIGITAL INPUT LOGIC DIGITAL INPUT LOOP POWERED ADC SPECIFICATIONS GENERAL SPECIFICATIONS TIMING CHARACTERISTICS SPI Timing Specifications Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS VOLTAGE OUTPUT CURRENT OUTPUT REFERENCE ADC SUPPLIES THEORY OF OPERATION ROBUST ARCHITECTURE SERIAL INTERFACE DAC ARCHITECTURE ADC OVERVIEW REFERENCE Reference Noise Charge Pump POWER-ON STATE OF THE AD74412R DEVICE FUNCTIONS High Impedance Interpreting ADC Data Voltage Output Mode Voltage Output Short-Circuit Protection Interpretin ADC Data Current Output Mode Current Output Open Circuit Detection Interpreting ADC Data Voltage Input Mode Selectable 200 kΩ to GND Interpreting ADC Data Current Input, Externally Powered Mode Short-Circuit Protection Interpreting ADC Data Current Input, Loop Powered Mode Short-Circuit Protection Interpreting ADC Data Resistance Measurement (External 2-Wire RTD) Interpreting ADC Data Digital Input Logic Interpreting ADC Data Digital Input Current Sink Digital Input Threshold Setting Debounce Function Debounce Mode 0 (Default) Debounce Mode 1 Digital Input Inverter DIGITAL INPUT, LOOP POWERED MODE Interpreting ADC Data GETTING STARTED USING CHANNEL FUNCTIONS Switching Channel Functions ADC FUNCTIONALITY ADC Conversion Rates ADC_RDYB Functionality ADC Output Data Format ADC Noise DIAGNOSTICS DACs LDAC Function Clear Code Function Digital Linear Slew Rate Control DRIVING INDUCTIVE LOADS RESET FUNCTION THERMAL ALERT AND THERMAL RESET FAULTS AND ALERTS Channel Faults POWER SUPPLY MONITORS GPO_x PINS SPI INTERFACE AND DIAGNOSTICS SPI CRC SPI Interface SCLK Count Feature Readback Mode Streaming Mode Auto Readback BOARD DESIGN AND LAYOUT CONSIDERATIONS APPLICATIONS INFORMATION REGISTER MAP NOP REGISTER FUNCTION SETUP REGISTER PER CHANNEL ADC CONFIGURATION REGISTER PER CHANNEL DIGITAL INPUT CONFIGURATION REGISTER PER CHANNEL GPO PARALLEL DATA REGISTER GPO CONFIGURATION REGISTER PER CHANNEL OUTPUT CONFIGURATION REGISTER PER CHANNEL DAC CODE REGISTER PER CHANNEL DAC CLEAR CODE REGISTER PER CHANNEL DAC ACTIVE CODE REGISTER PER CHANNEL DIGITAL INPUT THRESHOLD REGISTER ADC CONVERSION CONTROL REGISTER DIAGNOSTICS SELECT REGISTER DIGITAL OUTPUT LEVEL REGISTER ADC CONVERSION RESULTS REGISTER PER CHANNEL DIAGNOSTIC RESULTS REGISTERS PER DIAGNOSTIC CHANNEL ALERT STATUS REGISTER LIVE STATUS REGISTER ALERT MASK REGISTER READBACK SELECT REGISTER 80 SPS ADC CONVERSION CONTROL REGISTER THERMAL RESET ENABLE REGISTER COMMAND REGISTER SCRATCH OR SPARE REGISTER SILICON REVISION REGISTER OUTLINE DIMENSIONS ORDERING GUIDE