Datasheet AD5592R (Analog Devices) - 10

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AD5592R Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS BALL A1 INDICATOR 1 2 3 4 SDI SCLK RESET SYNC A GND I/O7 I/O0 VDD B I/O6 I/O3 I/O2 I/O1 C I/O4 SDO VREF I/O5 D AD5592R TOP VIEW
003
(BALL SIDE DOWN) Not to Scale
12506- Figure 5. AD5592R 16-Ball WLCSP Pin Configuration
Table 7. AD5592R 16 -Ball WLCSP Pin Function Descriptions Pin No. Mnemonic Description
A1 SDI Data In. Logic input. Data that is to be written to the DACs and control registers is provided on this input and is clocked into the register on the falling edge of SCLK. A2 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates of up to 50 MHz when writing to the DACs. SCLK has a maximum speed of 20 MHz when performing a conversion or clocking data from the AD5592R. A3 RESET Asynchronous Reset Pin. Tie this pin high for normal operation. When this pin is brought low, the AD5592R is reset to its default configuration. A4 SYNC Synchronization. Active low control input. SYNC is the frame synchronization signal for the input data. When SYNC goes low, data is transferred in on the falling edges of the next 16 clocks. B1 GND Ground Reference Point for All Circuitry on the AD5592R. B2 I/O7 Input/Output 7. This pin can be configured as a DAC, ADC, or general-purpose digital input or output. The function of this pin is determined by programming the I/Ox pin configuration registers (see Table 15 and Table 16). I/O7 can also be configured as a BUSY signal to indicate when an ADC conversion is taking place (see Table 30 and Table 31). B3, C4, C3, C2, I/O0 to I/O6 Input/Output 0 Through Input/Output 6. These pins can be independently configured as DACs, ADCs, or D1, D4, C1 general-purpose digital inputs or outputs. The function of each pin is determined by programming the I/Ox pin configuration registers (see Table 15 and Table 16). B4 VDD Power Supply Input. The AD5592R operates from 2.7 V to 5.5 V, and this pin must be decoupled with a 0.1 µF capacitor to GND. D2 SDO Data Out. Logic output. The conversion results from the ADC, register reads, and temperature sensor information are provided on this output as a serial data stream. The bits are clocked out on the rising edge of the SCLK input. The MSB is placed on the SDO pin on the falling edge of SYNC. Because the SCLK can idle high or low, the next bit is clocked out on the first rising edge of SCLK that follows a falling edge SCLK while SYNC is low (see Figure 4). D3 VREF Reference Input/Output. When the internal reference is enabled, the 2.5 V reference voltage is available on this pin. A 0.1 µF capacitor connected from the VREF pin to GND is recommended to achieve the specified performance from the AD5592R. When the internal reference is disabled, an external reference must be applied to this pin. The voltage range for the external reference is 1 V to VDD. Rev. E | Page 10 of 43 Document Outline Features Applications General Description Functional Block Diagram Revision History Functional Block Diagram (AD5592R-1) Specifications Timing Characteristics Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Terminology ADC Terminology DAC Terminology Theory of Operation DAC Section Resistor String Output Buffer ADC Section Calculating ADC Input Current GPIO Section Internal Reference RESETB Function Temperature Indicator Serial Interface Power-Up Time Write Mode Read Mode Configuring the AD5592R/AD5592R-1 General-Purpose Control Register DAC Write Operation LDAC Mode Operation DAC Readback ADC Operation Changing an ADC Sequence GPIO Operation Setting Pins as Outputs Setting Pins as Inputs Three-State Pins 85 kΩ Pull-Down Resistor Pins Power-Down Mode Reset Function Readback and LDAC Mode Register Applications Information Microprocessor Interfacing AD5592R/AD5592R-1 to SPI Interface AD5592R/AD5592R-1 to SPORT Interface Layout Guidelines Outline Dimensions Ordering Guide