Datasheet AD7292 (Analog Devices) - 8

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AD7292 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INF 7 6 5 4 3 2 1 0 IN IN IN IN IN IN IN IN RE V V V V V V V V 36 35 34 33 32 31 30 29 28 AV 1 DD 27 GPIO0/ALERT0 A 2 GND 26 GPIO1/ALERT1 D 3 25 GPIO2/DAC DISABLE0 GND 4 DV 24 GPIO3/LDAC DD AD7292 V 5 DRIVE 23 GPIO4/DAC DISABLE1 TOP VIEW CS 6 (Not to Scale) 22 GPIO5 SCLK 7 21 GPIO6/BUSY DIN 8 20 GPIO7 DOUT 9 19 REFOUT 10 11 12 13 14 15 16 17 18 3 2 1 0 D 1 0 T T T T 1 1 U U U U GN IO9 IO8 IO A IO VO VO VO VO GP GP GP GP NOTES
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1. THE EXPOSED PAD IS INTERNALLY CONNECTED TO AGND AND CAN BE SOLDERED TO THE GROUND PLANE OF THE SYSTEM.
0660 1 Figure 3. Pin Configuration
Table 8. Pin Function Descriptions Pin No. Mnemonic Description
1 AVDD Supply Pin. This pin should be decoupled to AGND with a 0.1 μF decoupling capacitor. 2, 14 AGND Analog Ground. Ground reference point for all analog circuitry on the AD7292. All analog signals should be referred to AGND. Both the AGND and DGND pins should be connected to the ground plane of the system. 3 DGND Digital Ground. Ground reference point for all digital circuitry on the AD7292. All digital signals should be referred to DGND. Both the DGND and AGND pins should be connected to the ground plane of the system. 4 DVDD Sets the GPIO voltage level. This pin should be decoupled to DGND with a 0.1 μF decoupling capacitor. 5 VDRIVE This pin sets the reference level of the SPI bus from 1.8 V to 5.25 V. This pin should be decoupled to DGND with a 0.1 μF decoupling capacitor. 6 CS Chip Select Signal. This active low logic input signal is used to frame the serial data input. 7 SCLK SPI Clock Input. 8 DIN SPI Serial Data Input. Serial data to be loaded into the registers of the AD7292 is provided on this pin. Data is clocked into the serial interface on the falling edge of SCLK. 9 DOUT SPI Serial Data Output. Serial data to be read from the registers of the AD7292 is provided on this pin. Data is clocked out on the rising edge of SCLK. DOUT is high impedance when it is not outputting data. 10 to 13 VOUT3 to VOUT0 Buffered DAC Analog Outputs. Each DAC analog output is driven from an output amplifier and has a maximum output voltage span of 5 V. Each DAC is capable of sourcing and sinking 10 mA and driving a 1 nF load. 15 to 18 GPIO11 to GPIO8 General-Purpose Input/Output Pins. 19 REFOUT ADC Internal Reference Output. Decouple the internal ADC reference buffer to AGND with a 0.1 μF decoupling capacitor. 20 GPIO7 General-Purpose Input/Output Pin. 21 GPIO6/BUSY General-Purpose Input/Output Pin (GPIO6). Busy Output Pin (BUSY). When a conversion starts, this output pin transitions high and remains high until the conversion is completed. 22 GPIO5 General-Purpose Input/Output Pin. 23 GPIO4/ General-Purpose Input/Output Pin (GPIO4). DAC DISABLE1 DAC Disable Pin 1 (DAC DISABLE1). When this pin is activated, the selected DAC outputs are disabled. Select the DAC channels to be disabled by this pin using the GPIO4/DAC DISABLE1 subregister within the configuration register bank (see Table 30). 24 GPIO3/LDAC General-Purpose Input/Output Pin (GPIO3). LDAC Input Pin (LDAC). When this input is taken high, the DAC registers are updated. 25 GPIO2/ General-Purpose Input/Output Pin (GPIO2). DAC DISABLE0 DAC Disable Pin 0 (DAC DISABLE0). When this pin is activated, the selected DAC outputs are disabled. Select the DAC channels to be disabled by this pin using the GPIO2/DAC DISABLE0 subregister within the configuration register bank (see Table 29). Rev. A | Page 8 of 40 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications ADC Specifications DAC Specifications General Specifications Temperature Sensor Specifications Timing Specifications Timing Diagram Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Analog Inputs Single-Ended Mode Differential Mode ADC Transfer Functions Temperature Sensor DAC Operation Digital I/O Pins GPIO0/ALERT0 and GPIO1/ALERT1 Pins GPIO2/DAC DISABLE0 and GPIO4/DAC DISABLE1 Pins GPIO3/LDAC Pin GPIO6/BUSY Pin Serial Port Interface (SPI) Interface Protocol Register Structure Register Descriptions Vendor ID Register (Address 0x00) ADC Data Register (Address 0x01) ADC Sequence Register (Address 0x03) Configuration Register Bank (Address 0x05) Digital Output Driver Subregister (Address 0x01) Digital I/O Function Subregister (Address 0x02) General Subregister (Address 0x08) VIN RANGE0 and VIN RANGE1 Subregisters (Address 0x10 and Address 0x11) ADC Sampling Mode Subregister (Address 0x12) VIN Filter Subregister (Address 0x13) Conversion Delay Control Subregister (Address 0x14) VIN ALERT0 Routing and VIN ALERT1 Routing Subregisters (Address 0x15 and Address 0x16) Temperature Sensor Subregister (Address 0x20) Temperature Sensor Alert Routing Subregister (Address 0x21) GPIO2/DAC DISABLE0 and GPIO4/DAC DISABLE1 Subregisters (Address 0x30 and Address 0x31) Alert Limits Register Bank (Address 0x06) Alert High Limit and Alert Low Limit Subregisters Hysteresis Subregisters Alert Flags Register Bank (Address 0x07) ADC Alert Flags and TSENSE Alert Flags Subregisters (Address 0x00 and Address 0x02) Minimum and Maximum Register Bank (Address 0x08) Offset Register Bank (Address 0x09) DAC Buffer Enable Register (Address 0x0A) GPIO Register (Address 0x0B) Conversion Command Register (Address 0x0E) ADC Conversion Result Registers, VIN0 to VIN7 (Address 0x10 to Address 0x17) TSENSE Conversion Result Register (Address 0x20) DAC Channel Registers (Address 0x30 to Address 0x33) ADC Conversion Control ADC Conversion Command ADC Sequencer DAC Output Control LDAC Operation Simultaneous Update of All DAC Outputs Alerts and Limits Alert Limit Monitoring Features Hysteresis Hardware Alert Pins Alert Flag Bits in the Conversion Result Registers Alert Flags Register Bank Minimum and Maximum Conversion Results Outline Dimensions Ordering Guide