Datasheet AD5590 (Analog Devices) - 4
| 制造商 | Analog Devices |
| 描述 | 16 Input, 16 Output Analog I/O Port with Integrated Amplifiers |
| 页数 / 页 | 44 / 4 — AD5590. SPECIFICATIONS ADC SPECIFICATIONS. Table 1. Parameter. Min. Typ. … |
| 修订版 | A |
| 文件格式/大小 | PDF / 1.0 Mb |
| 文件语言 | 英语 |
AD5590. SPECIFICATIONS ADC SPECIFICATIONS. Table 1. Parameter. Min. Typ. Max. Unit. Test Conditions/Comments2
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AD5590 SPECIFICATIONS ADC SPECIFICATIONS
ADCV 1 DD = VDRIVE = 2.7 V to 5.25 VREFA = 2.5 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless otherwise noted.
Table 1. Parameter Min Typ Max Unit Test Conditions/Comments2
DYNAMIC PERFORMANCE fIN = 50 kHz sine wave, fSCLK = 20 MHz Signal-to-(Noise + Distortion) (SINAD)3 68.5 70 dB @ 5 V 70.5 dB @ 3 V Signal-to-Noise Ratio (SNR)3 69 70 dB @ 5 V 70.5 dB @ 3 V Total Harmonic Distortion (THD)3 −74 −82 dB @ 5 V −82 dB @ 3 V Peak Harmonic or Spurious Noise (SFDR)3 −75 −86 dB @ 5 V −80 dB @ 3 V Intermodulation Distortion (IMD)3, 4 fa = 40.1 kHz, fb = 41.5 kHz Second-Order Terms −85 dB Third-Order Terms −85 dB Aperture Delay4 10 ns Aperture Jitter4 50 ps Channel-to-Channel Isolation3, 4 −82 dB fIN = 400 kHz Full Power Bandwidth4 8.2 MHz @ 3 dB 1.6 MHz @ 0.1 dB DC ACCURACY3 Resolution 12 Bits Integral Nonlinearity −1 +1 LSB Differential Nonlinearity −1 +1.5 LSB Guaranteed no missing codes to 12 bits 0 V to VREFA Input Range Straight binary output coding Offset Error −10 ±0.6 +10 LSB Offset Error Match 3.5 LSB Gain Error −2 +2 LSB Gain Error Match −0.8 +0.8 LSB 0 V to 2 × VREFA Input Range −VREFA to +VREFA biased about VREFA with twos complement output coding offset Positive Gain Error −2 +2 LSB Positive Gain Error Match −0.8 +0.8 LSB Zero-Code Error −8 ±0.6 +8 LSB Zero-Code Error Match 2 LSB Negative Gain Error −1 +1 LSB Negative Gain Error Match −0.8 +0.8 LSB ANALOG INPUT Input Voltage Ranges 0 to VREFA V Range bit set to 1 0 to 2 × VREFA V Range bit set to 0, ADCVDD/VDRIVE = 4.75 V to 5.25 V for 0 V to 2 × VREFAS DC Leakage Current −1 +1 µA Input Capacitance4 20 pF REFERENCE INPUT VREFA Input Voltage 2.5 V ±1% specified performance DC Leakage Current −1 +1 µA VREFA Input Impedance4 36 kΩ fSAMPLE = 1 MSPS Rev. A | Page 4 of 44 Document Outline Features Applications Functional Block Diagram Revision History General Description Specifications ADC Specifications DAC Specifications DAC AC Characteristics Operational Amplifier Specifications Timing Specifications ADC Timing Characteristics DAC Timing Characteristics Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics DAC ADC Amplifier Terminology Theory of Operation DAC Section Resistor String DAC Internal Reference DAC Output Amplifier ADC Section ADC Converter Operation Analog Input ADC Transfer Function Analog Input Selection Digital Inputs VDRIVE Reference Section Amplifier Section Serial Interface Accessing the DAC Block DAC Input Shift Register Interrupt DAC Internal Reference Register DAC Power-On Reset DAC Power-Down Modes DAC Clear Code Register LDAC Function Accessing the ADC Block ADC Modes of Operation Normal Mode (PM1 = PM0 = 1) Full Shutdown (PM1 = 1, PM0 = 0) AutoShutdown (PM1 = 0, PM0 = 1) Autostandby (PM1 = PM0 = 0) Powering Up the ADC Interfacing to the ADC ADC Control Register ADC Sequencer Operation ADC Shadow Register ADC Power vs. Throughput Rate Outline Dimensions Ordering Guide
AD5590 SPECIFICATIONS ADC SPECIFICATIONS
ADCV 1 DD = VDRIVE = 2.7 V to 5.25 VREFA = 2.5 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless otherwise noted.
Table 1. Parameter Min Typ Max Unit Test Conditions/Comments2
DYNAMIC PERFORMANCE fIN = 50 kHz sine wave, fSCLK = 20 MHz Signal-to-(Noise + Distortion) (SINAD)3 68.5 70 dB @ 5 V 70.5 dB @ 3 V Signal-to-Noise Ratio (SNR)3 69 70 dB @ 5 V 70.5 dB @ 3 V Total Harmonic Distortion (THD)3 −74 −82 dB @ 5 V −82 dB @ 3 V Peak Harmonic or Spurious Noise (SFDR)3 −75 −86 dB @ 5 V −80 dB @ 3 V Intermodulation Distortion (IMD)3, 4 fa = 40.1 kHz, fb = 41.5 kHz Second-Order Terms −85 dB Third-Order Terms −85 dB Aperture Delay4 10 ns Aperture Jitter4 50 ps Channel-to-Channel Isolation3, 4 −82 dB fIN = 400 kHz Full Power Bandwidth4 8.2 MHz @ 3 dB 1.6 MHz @ 0.1 dB DC ACCURACY3 Resolution 12 Bits Integral Nonlinearity −1 +1 LSB Differential Nonlinearity −1 +1.5 LSB Guaranteed no missing codes to 12 bits 0 V to VREFA Input Range Straight binary output coding Offset Error −10 ±0.6 +10 LSB Offset Error Match 3.5 LSB Gain Error −2 +2 LSB Gain Error Match −0.8 +0.8 LSB 0 V to 2 × VREFA Input Range −VREFA to +VREFA biased about VREFA with twos complement output coding offset Positive Gain Error −2 +2 LSB Positive Gain Error Match −0.8 +0.8 LSB Zero-Code Error −8 ±0.6 +8 LSB Zero-Code Error Match 2 LSB Negative Gain Error −1 +1 LSB Negative Gain Error Match −0.8 +0.8 LSB ANALOG INPUT Input Voltage Ranges 0 to VREFA V Range bit set to 1 0 to 2 × VREFA V Range bit set to 0, ADCVDD/VDRIVE = 4.75 V to 5.25 V for 0 V to 2 × VREFAS DC Leakage Current −1 +1 µA Input Capacitance4 20 pF REFERENCE INPUT VREFA Input Voltage 2.5 V ±1% specified performance DC Leakage Current −1 +1 µA VREFA Input Impedance4 36 kΩ fSAMPLE = 1 MSPS Rev. A | Page 4 of 44 Document Outline Features Applications Functional Block Diagram Revision History General Description Specifications ADC Specifications DAC Specifications DAC AC Characteristics Operational Amplifier Specifications Timing Specifications ADC Timing Characteristics DAC Timing Characteristics Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics DAC ADC Amplifier Terminology Theory of Operation DAC Section Resistor String DAC Internal Reference DAC Output Amplifier ADC Section ADC Converter Operation Analog Input ADC Transfer Function Analog Input Selection Digital Inputs VDRIVE Reference Section Amplifier Section Serial Interface Accessing the DAC Block DAC Input Shift Register Interrupt DAC Internal Reference Register DAC Power-On Reset DAC Power-Down Modes DAC Clear Code Register LDAC Function Accessing the ADC Block ADC Modes of Operation Normal Mode (PM1 = PM0 = 1) Full Shutdown (PM1 = 1, PM0 = 0) AutoShutdown (PM1 = 0, PM0 = 1) Autostandby (PM1 = PM0 = 0) Powering Up the ADC Interfacing to the ADC ADC Control Register ADC Sequencer Operation ADC Shadow Register ADC Power vs. Throughput Rate Outline Dimensions Ordering Guide