Datasheet ADL5902 (Analog Devices) - 9

Data Sheet ADL5902 TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V, ZO = 50 Ω, single-ended input drive, VOUT connected to VSET, VTGT = 0.8 V, CLPF = 0.1 μF, TA = +25°C (black), −40°C (blue), +85°C (red), +125°C (orange) where appropriate. Error referred to the best fit line (linear regression) from − 10 dBm to − 40 dBm, unless otherwise indicated. Input RF signal is a sine wave (CW), unless otherwise indicated.
6.0 6 6.0 6 T V ADJ = 0.5V TADJ = 0.5V 5.5 CALIBRATION AT 0dBm, –45dBm, AND –60dBm 5 5.5 REPRESENTS 55 DEVICES FROM 2 LOTS 5 5.0 4 5.0 4 4.5 3 4.5 3 ) ) (V V 4.0 2 ( 4.0 2 E E 3.5 1 B) B) d 3.5 1 d TAG LTAG L 3.0 0 R ( O 3.0 0 R ( VO RO V T 2.5 UT –1 R 2.5 –1 RRO E U P E P T T 2.0 U –2 2.0 –2 O OU 1.5 –3 1.5 –3 1.0 –4 1.0 –4 0.5 –5 0.5 –5 0 –6 0 –6
3
–60 –50 –40 –30 –20 –10 0 10
00
–60 –50 –40 –30 –20 –10 0 10
06 8- 0 8- 821
PIN (dBm) P
21 0
IN (dBm)
08 Figure 3. Typical VOUT and Log Conformance Error with Respect to 25°C Ideal Figure 6. Distribution of Error with Respect to 25°C over Temperature vs. Line over Temperature vs. Input Amplitude at 100 MHz, CW Input Amplitude, CW, Frequency = 100 MHz
6.0 6 6.0 6 TADJ = 0.4V VTADJ = 0.4V 5.5 CALIBRATION AT 0dBm, –45dBm, AND –60dBm 5 5.5 REPRESENTS 55 DEVICES FROM 2 LOTS 5 5.0 4 5.0 4 4.5 3 4.5 3 ) ) V V ( 4.0 2 ( 4.0 2 E E 3.5 1 B) B) d 3.5 1 d TAG LTAG L O 3.0 0 R ( O 3.0 0 R ( V V T UT 2.5 –1 RRO 2.5 –1 RRO E U P E P 2.0 T UT –2 2.0 –2 O OU 1.5 –3 1.5 –3 1.0 –4 1.0 –4 0.5 –5 0.5 –5 0 –6 0 –6
4
–60 –50 –40 –30 –20 –10 0 10
00
–60 –50 –40 –30 –20 –10 0 10
07 0 8- 8- 21
PIN (dBm) P
08
IN (dBm)
821 0 Figure 4. Typical VOUT and Log Conformance Error with Respect to 25°C Ideal Figure 7. Distribution of Error with Respect to 25°C over Temperature vs. Line over Temperature vs. Input Amplitude at 700 MHz, CW Input Amplitude, CW, Frequency = 700 MHz
6.0 6 6.0 6 T VTADJ = 0.4V 5.5 ADJ = 0.4V 5 CALIBRATION AT 0dBm, –45dBm, AND –60dBm 5.5 REPRESENTS 55 DEVICES FROM 2 LOTS 5 5.0 4 5.0 4 4.5 3 4.5 3 ) ) V 4.0 2 (V 4.0 2 E ( E 3.5 1 B) B) d 3.5 1 d LTAG ( LTAG 3.0 0 R O 3.0 0 R ( VO RO V T 2.5 –1 R U 2.5 –1 RRO E UT P E P T 2.0 –2 U 2.0 –2 UT O O 1.5 –3 1.5 –3 1.0 –4 1.0 –4 0.5 –5 0.5 –5
5
0 –6 0 –6
-00 8
–60 –50 –40 –30 –20 –10 0 10 –60 –50 –40 –30 –20 –10 0 10
08 21 0 08 8-
PIN (dBm) PIN (dBm)
21 08 Figure 5. Typical VOUT and Log Conformance Error with Respect to 25°C Ideal Figure 8. Distribution of Error with Respect to 25°C over Temperature vs. Line over Temperature vs. Input Amplitude at 900 MHz, CW Input Amplitude, CW, Frequency = 900 MHz Rev. B | Page 9 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION SQUARE LAW DETECTOR AND AMPLITUDE TARGET RF INPUT INTERFACE SMALL SIGNAL LOOP RESPONSE TEMPERATURE SENSOR INTERFACE VREF INTERFACE TEMPERATURE COMPENSATION INTERFACE POWER-DOWN INTERFACE VSET INTERFACE OUTPUT INTERFACE VTGT INTERFACE BASIS FOR ERROR CALCULATIONS MEASUREMENT MODE BASIC CONNECTIONS SETTING VTADJ SETTING VTGT CHOOSING A VALUE FOR CLPF OUTPUT VOLTAGE SCALING SYSTEM CALIBRATION AND ERROR CALCULATION HIGH FREQUENCY PERFORMANCE LOW FREQUENCY PERFORMANCE DESCRIPTION OF CHARACTERIZATION EVALUATION BOARD SCHEMATICS AND ARTWORK ASSEMBLY DRAWINGS OUTLINE DIMENSIONS ORDERING GUIDE