Datasheet ADRV9026 (Analog Devices) - 6

ADRV9026 Data Sheet Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Error Vector Magnitude EVM PLL optimized for narrow-band noise, measured using LTE 20 MHz signal 800 MHz LO 0.38 % 50 kHz PLL bandwidth 1800 MHz LO 0.60 % 50 kHz PLL bandwidth 2600 MHz LO 0.44 % 500 kHz PLL bandwidth 3800 MHz LO 0.53 % 200 kHz PLL bandwidth 4800 MHz LO 0.63 % 400 kHz PLL bandwidth 5700 MHz LO 0.84 % 500 kHz PLL bandwidth Transmitter Time Division Duplex TDD Time from SPI_EN Going High tSCH 12 ns to Change in Tx Attenuation Time Between Consecutive tACH 20 ns A large change in attenuation can be Microattenuation Steps segmented into a series of smaller attenuation changes Attenuation Overshoot During 0.1 dB Transition Change in Attenuation per 0.1 dB Microstep RECEIVERS Rx Center Frequency 650 6000 MHz Gain Range 30 dB Attenuation Accuracy Analog Gain Step 0.5 dB Attenuator steps from 0 dB to 6 dB 1 dB Attenuator steps from 6 dB to 30 dB Residual Gain Step Error 0.1 dB Gain Temperature Slope −6.4 mdB/°C Internal LO Delay Temperature 1.0 ps/°C Slope Frequency Response Peak-to-Peak Gain Deviation 1 dB 200 MHz bandwidth, includes compensation by programmable FIR filter 0.2 dB Any 20 MHz span, includes compensation by programmable FIR filter Rx Bandwidth 200 MHz Zero IF mode Rx Alias Band Rejection 80 dB Due to digital filters Maximum Useable Input Level PHIGH −11 dBm This continuous wave signal level corresponds to the input power that produces −2 dBFS at the digital output with 0 dB channel attenuation 800 MHz −12.4 dBm 1800 MHz −12.7 dBm 2600 MHz −11.9 dBm 3800 MHz −11.0 dBm 4800 MHz −12.0 dBm 5700 MHz −11.1 dBm Maximum Source VSWR 3 Input Impedance ZIN 100 Ω Differential Input Port\Return Loss 10 dB Unmatched differential port return loss Noise Figure NF 0 dB attenuation, at receiver port 800 MHz 11 dB 1800 MHz 11.5 dB 2600 MHz 11.9 dB 3800 MHz 12.8 dB 4800 MHz 13.3 dB 5700 MHz 14.5 dB Rev. A | Page 6 of 118 Document Outline Features Applications General Description Revision History Functional Block Diagram Specifications Transmitters and Receivers Synthesizers, Auxiliary Converters, and Clock References Digital Specifications Power Supply Specifications Current Consumption TDD Operation—Four Receiver Channels Enabled TDD Operation—Four Transmitter and One Observation Receiver Channels Enabled FDD Operation—LO1 and LO2, Four Receiver, Four Transmitter, and One Observation Receiver Channels Enabled Digital Interface and Timing Specifications Absolute Maximum Ratings Junction Temperature Reflow Profile Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics 800 MHz Band 1800 MHz Band 2600 MHz Band 3800 MHz Band 4800 MHz Band 5700 MHz Band Theory of Operation General Transmitter Receiver Observation Receiver Clock Input Synthesizers RF Synthesizers Auxiliary Synthesizer Clock Synthesizer SPI Interface GPIO_x Pins Auxiliary Converters GPIO_ANA_x/AUXDAC_x AUXADC_x JTAG Boundary Scan Applications Information Power Supply Sequence Data Interface Outline Dimensions Ordering Guide