Datasheet ADRV9008-2 (Analog Devices) - 9

Data Sheet ADRV9008-2 Parameter Symbol Min Typ Max Unit Test Conditions/Comments
EXTERNAL LO INPUT Input Frequency fEXTLO 300 8000 MHz Input frequency must be 2× the desired LO frequency Input Signal Power 0 12 dBm 50 Ω matching at the source 3 dBm fEXTLO ≤ 2 GHz, add 0.5 dBm/GHz above 2 GHz 6 dBm fEXTLO = 8 GHz External LO Input Signal To ensure adequate QEC Differential Phase Error 3.6 ps Amplitude Error 1 dB Duty Cycle Error 2 % Even-Order Harmonics −50 dBc CLOCK SYNTHESIZER Integrated Phase Noise 1 kHz to 100 MHz 1966.08 MHz LO 0.4 °rms PLL optimized for close in phase noise Spot Phase Noise 1966.08 MHz LO 100 kHz Offset −109 dBc/Hz 1 MHz Offset −129 dBc/Hz 10 MHz Offset −149 dBc/Hz REFERENCE CLOCK (REF_CLK_IN±) Frequency Range 10 1000 MHz Signal Level 0.3 2.0 V p-p AC-coupled, common-mode voltage (VCM) = 618 mV, for best spurious performance, use <1 V p-p input clock AUXILIARY CONVERTERS ADC Resolution 12 Bits Input Voltage Minimum 0.05 V Maximum VDDA_ V 3P3 − 0.05 DAC Resolution 10 Bits Includes four offset levels Output Voltage Minimum 0.7 V 1 V VREF Maximum VDDA_ V 2.5 V VREF 3P3 − 0.3 Output Drive Capability 10 mA DIGITAL SPECIFICATIONS (CMOS)—SDIO, SDO, SCLK, CS GPIO_x, TXx_ENABLE, ORXx_ENABLE Logic Inputs Input Voltage High Level VDD_ VDD_INTERFACE V INTERFACE × 0.8 Low Level 0 VDD_ V INTERFACE × 0.2 Input Current Rev. 0 | Page 9 of 95 Document Outline Features Applications General Description Revision History Functional Block Diagram Specifications Current and Power Consumption Specifications Timing Diagrams Absolute Maximum Ratings Reflow Profile Thermal Management Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics 75 MHz to 525 MHz Band 650 MHz to 3000 MHz Band 3400 MHz to 4800 MHz Band 5100 MHz to 5900 MHz Band Transmitter Output Impedance Observation Receiver Input Impedance Terminology Theory of Operation Transmitter Observation Receiver Clock Input Synthesizers RF PLL Clock PLL Serial Peripheral Interface (SPI) JTAG Boundary Scan Power Supply Sequence GPIO_x Pins Auxiliary Converters AUXADC_x Auxiliary DAC x JESD204B Data Interface Applications Information PCB Layout and Power Supply Recommendations Overview PCB Material and Stackup Selection Fanout and Trace Space Guidelines Component Placement and Routing Guidelines Signals with Highest Routing Priority Signals with Second Routing Priority Signals with Lowest Routing Priority RF and JESD204B Transmission Line Layout RF Routing Guidelines Transmitter Balun DC Feed Supplies JESD204B Trace Routing Recommendations Routing Recommendations Stripline Transmission Lines vs. Microstrip Transmission Lines Isolation Techniques Used on the ADRV9008-2W/PCBZ Isolation Goals Isolation Between JESD204B Lines RF Port Interface Information RF Port Impedance Data Advanced Design System (ADS) Setup Using the DataAccessComponent and SEDZ File Transmitter Bias and Port Interface General Observation Receiver Path Interface Impedance Matching Network Example Outline Dimensions Ordering Guide