Datasheet ADRV9008-1 (Analog Devices) - 9
| 制造商 | Analog Devices |
| 描述 | Integrated Dual RF Receiver |
| 页数 / 页 | 68 / 9 — Data Sheet. ADRV9008-1. TIMING DIAGRAMS. AT DEVICE PINS. REF_CLK_IN± … |
| 文件格式/大小 | PDF / 1.9 Mb |
| 文件语言 | 英语 |
Data Sheet. ADRV9008-1. TIMING DIAGRAMS. AT DEVICE PINS. REF_CLK_IN± DELAY. AT DEVICE CORE. IN REFERENCE TO SYSREF_IN±. t’S
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Data Sheet ADRV9008-1 TIMING DIAGRAMS AT DEVICE PINS REF_CLK_IN± DELAY AT DEVICE CORE IN REFERENCE TO SYSREF_IN± t t’ t’ H tH H H tS tS t’S t’S REF_CLK_IN± t CLK DELAY = 2ns H = –1.5ns t’H = +0.5ns tS = +2.5ns t’S = +0.5ns NOTES 1. tH AND tS ARE THE HOLD AND SETUP TIMES FOR THE REF_CLK_IN± PINS. t’H AND t’S REFER TO THE
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DELAYED HOLD AND SETUP TIMES AT THE DEVICE CORE IN REFERENCE TO THE SYSREF_N± SIGNALS DUE TO AN INTERNAL BUFFER THAT THE SIGNAL PASSES THROUGH.
16830- Figure 2. SYSREF_IN± Setup and Hold Timing
tH tH tH tH tS tS tS tS REF_CLK_IN± SYSREF_IN± t
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H = –1.5ns VALID SYSREF INVALID SYSREF tS = +2.5ns
16830- Figure 3. SYSREF_IN± Setup and Hold Timing Examples, Relative to Device Clock Rev. 0 | Page 9 of 68 Document Outline Features Applications General Description Revision History Functional Block Diagram Specifications Current and Power Consumption Specifications Timing Diagrams Absolute Maximum Ratings Reflow Profile Thermal Management Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics 75 MHz to 525 MHz Band 650 MHz to 3000 MHz Band 3400 MHz to 4800 MHz Band 5100 MHz to 5900 MHz Band Receiver Input Impedance Terminology Theory of Operation Receivers Clock Input Synthesizers RF PLL Clock PLL SPI JTAG Boundary Scan Power Supply Sequence GPIO_x Pins Auxiliary Converters AUXADC_x Auxiliary DAC x JESD204B Data Interface Applications Information PCB Layout and Power Supply Recommendations Overview PCB Material and Stackup Selection Fanout and Trace Space Guidelines Component Placement and Routing Guidelines Signals with Highest Routing Priority Signals with Second Routing Priority Signals with Lowest Routing Priority RF and JESD204B Transmission Line Layout RF Routing Guidelines JESD204B Trace Routing Recommendations Routing Recommendations Stripline Transmission Lines vs. Microstrip Transmission Lines Isolation Techniques Used on the ADRV9008-1W/PCBZ Isolation Goals Isolation Between JESD204B Lines RF Port Interface Information RF Port Impedance Data Advanced Design System (ADS) Setup Using the DataAccessComponent and SEDZ File General Receiver Path Interface Impedance Matching Network Examples Outline Dimensions Ordering Guide
005
DELAYED HOLD AND SETUP TIMES AT THE DEVICE CORE IN REFERENCE TO THE SYSREF_N± SIGNALS DUE TO AN INTERNAL BUFFER THAT THE SIGNAL PASSES THROUGH.
16830- Figure 2. SYSREF_IN± Setup and Hold Timing
tH tH tH tH tS tS tS tS REF_CLK_IN± SYSREF_IN± t
006
H = –1.5ns VALID SYSREF INVALID SYSREF tS = +2.5ns
16830- Figure 3. SYSREF_IN± Setup and Hold Timing Examples, Relative to Device Clock Rev. 0 | Page 9 of 68 Document Outline Features Applications General Description Revision History Functional Block Diagram Specifications Current and Power Consumption Specifications Timing Diagrams Absolute Maximum Ratings Reflow Profile Thermal Management Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics 75 MHz to 525 MHz Band 650 MHz to 3000 MHz Band 3400 MHz to 4800 MHz Band 5100 MHz to 5900 MHz Band Receiver Input Impedance Terminology Theory of Operation Receivers Clock Input Synthesizers RF PLL Clock PLL SPI JTAG Boundary Scan Power Supply Sequence GPIO_x Pins Auxiliary Converters AUXADC_x Auxiliary DAC x JESD204B Data Interface Applications Information PCB Layout and Power Supply Recommendations Overview PCB Material and Stackup Selection Fanout and Trace Space Guidelines Component Placement and Routing Guidelines Signals with Highest Routing Priority Signals with Second Routing Priority Signals with Lowest Routing Priority RF and JESD204B Transmission Line Layout RF Routing Guidelines JESD204B Trace Routing Recommendations Routing Recommendations Stripline Transmission Lines vs. Microstrip Transmission Lines Isolation Techniques Used on the ADRV9008-1W/PCBZ Isolation Goals Isolation Between JESD204B Lines RF Port Interface Information RF Port Impedance Data Advanced Design System (ADS) Setup Using the DataAccessComponent and SEDZ File General Receiver Path Interface Impedance Matching Network Examples Outline Dimensions Ordering Guide