Datasheet HMC8200LP5ME (Analog Devices) - 7

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Data Sheet HMC8200LP5ME PIN CONFIGURATION AND FUNCTION DESCRIPTIONS RM NV K P N _P DI CL CC_I CC_E NV S S SEN LO_ LO_ V V E 32 31 30 29 28 27 26 25 SDO 1 24 ENV_N DVDD 2 23 D2S_OUT RST 3 22 VCC_D2S HMC8200 BB_IP 4 21 VVA_IN TOP VIEW BB_IN 5 20 VGA_VCTRL (Not to Scale) VCC_DGA 6 19 VCC_VGA BB_QN 7 18 TX_OUT BB_QP 8 17 VCC_AMP 9 1 10 1 12 13 14 15 16 N IF F G UT UT R IFIN O _ 2_I 1_O TX D_O CC_BG A_S LOG_ P V LOG_ CC_L L A_S V DG S DG
100
NOTES 1. CONNECT EXPOSED GROUND PADDLE TO RF/DC GROUND.
13868- Figure 2. Pin Configuration
Table 5. Pin Function Descriptions Pin No. Mnemonic Description
1 SDO SPI Serial Data Output. 2 DVDD SPI Digital Supply (3.3 VDC). Refer to Figure 64 for the required external components. 3 RST SPI Reset. Connect to logic high for normal operation. 4, 5 BB_IP, BB_IN Positive and Negative Filter Baseband IF I Inputs. 6 VCC_DGA Power Supply for the Digital Variable Gain Amplifier (3.3 VDC). Refer to Figure 64 for the required external components. 7, 8 BB_QN, BB_QP Negative and Positive Filter Baseband IF Q Inputs. 9 TX_IFIN Transmit (Tx) IF Input, Intermediate Frequency Input Port. This pin is matched to 50 Ω. 10 DGA_S1_OUT Power Supply for the First Stage Digital Gain Amplifier (3.3 VDC). This pin is matched to 50 Ω. Refer to Figure 64 for the required external components. 11 DGA_S2_IN Second Stage Digital Gain Amplifier Input. 12 LOG_IF IF Log Detector Output. 13 SLPD_OUT Square Law Detector Output. 14 VCC_BG Band Gap Supply. Power Supply Voltage for the Bias Controller (3.3 VDC). Refer to Figure 64 for the required external components. 15 LOG_RF RF Log Detector Output. 16 VCC_LOG RF Log Detector Supply (3.3 VDC). Refer to Figure 64 for the required external components. 17 VCC_AMP Power Supply for the RF Output Amplifier (3.3 VDC). Refer to Figure 64 for the required external components. 18 TX_OUT Tx Chip Output. 19 VCC_VGA Power Supply for the Variable Gain Amplifier (3.3 VDC). Refer to Figure 64 for the required external components. 20 VGA_VCTRL VGA Control Voltage. Refer to Figure 64 for the required external components. 21 VVA_IN VVA Intermediate Frequency Input Port. This pin is matched to 50 Ω. 22 VCC_D2S Differential to Single Amplifier Supply. Refer to Figure 64 for the required external components. 23 D2S_OUT Differential to Single Amplifier Intermediate Frequency Output Port. This pin is matched to 50 Ω. 24, 25 ENV_N, ENV_P Envelope Detector Outputs. 26 VCC_ENV Envelope Detector Supply (3.3 VDC). Refer to Figure 64 for the required external components. 27 VCC_IRM Power Supply for the Mixer Output (3.3 VDC). Refer to Figure 64 for the required external components. 28, 29 LO_N, LO_P Local Oscillator Inputs. These pins are ac-coupled and matched to 50 Ω. 30 SEN SPI Serial Enable. 31 SCLK SPI Clock Digital Input. 32 SDI SPI Serial Data Input. EPAD Exposed Pad. Connect exposed ground paddle to RF/dc ground. Rev. D | Page 7 of 25 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Electrical Characteristics: 800 MHz to 1800 MHz RF Frequency Range Electrical Characteristics: 1800 MHz to 2800 MHz RF Frequency Range Electrical Characteristics: 2800 MHz to 4000 MHz RF Frequency Range Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Register Array Assignments and Serial Interface Read Example Register Descriptions Register Array Assignments Enable Bits Digital Gain Amplifier: DGA Control Digital Gain Amplifier: Amplifier Current, Envelope Level, and VGA Attenuation Bias Image Reject Mixer: Sideband, and Polarity and Offset for I Image Reject Mixer: Polarity and Offset for Q Phase I: Adjust Phase Q: Adjust Evaluation Printed Circuit Board (PCB) Evaluation PCB Schematic Outline Dimensions Ordering Guide