Datasheet AD9361 (Analog Devices) - 8

AD9361 Data Sheet CURRENT CONSUMPTION—VDD_INTERFACE Table 2. VDD_INTERFACE = 1.2 V Parameter Min Typ Max Unit Test Conditions/Comments
SLEEP MODE 45 µA Power applied, device disabled 1RX, 1TX, DDR LTE10 Single Port 2.9 mA 30.72 MHz data clock, CMOS Dual Port 2.7 mA 15.36 MHz data clock, CMOS LTE20 Dual Port 5.2 mA 30.72 MHz data clock, CMOS 2RX, 2TX, DDR LTE3 Dual Port 1.3 mA 7.68 MHz data clock, CMOS LTE10 Single Port 4.6 mA 61.44 MHz data clock, CMOS Dual Port 5.0 mA 30.72 MHz data clock, CMOS LTE20 Dual Port 8.2 mA 61.44 MHz data clock, CMOS GSM Dual Port 0.2 mA 1.08 MHz data clock, CMOS WiMAX 8.75 Dual Port 3.3 mA 20 MHz data clock, CMOS WiMAX 10 Single Port TDD RX 0.5 mA 22.4 MHz data clock, CMOS TDD TX 3.6 mA 22.4 MHz data clock, CMOS FDD 3.8 mA 44.8 MHz data clock, CMOS WiMAX 20 Dual Port FDD 6.7 mA 44.8 MHz data clock, CMOS
Table 3. VDD_INTERFACE = 1.8 V Parameter Min Typ Max Unit Test Conditions/Comments
SLEEP MODE 84 μA Power applied, device disabled 1RX, 1TX, DDR LTE10 Single Port 4.5 mA 30.72 MHz data clock, CMOS Dual Port 4.1 mA 15.36 MHz data clock, CMOS LTE20 Dual Port 8.0 mA 30.72 MHz data clock, CMOS 2RX, 2TX, DDR LTE3 Dual Port 2.0 mA 7.68 MHz data clock, CMOS LTE10 Single Port 8.0 mA 61.44 MHz data clock, CMOS Dual Port 7.5 mA 30.72 MHz data clock, CMOS LTE20 Dual Port 14.0 mA 61.44 MHz data clock, CMOS GSM Dual Port 0.3 mA 1.08 MHz data clock, CMOS WiMAX 8.75 Dual Port 5.0 mA 20 MHz data clock, CMOS Rev. F | Page 8 of 36 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS CURRENT CONSUMPTION—VDD_INTERFACE CURRENT CONSUMPTION—VDDD1P3_DIG AND VDDAx (COMBINATION OF ALL 1.3 V SUPPLIES) ABSOLUTE MAXIMUM RATINGS REFLOW PROFILE THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS 800 MHz FREQUENCY BAND 2.4 GHz FREQUENCY BAND 5.5 GHz FREQUENCY BAND THEORY OF OPERATION GENERAL RECEIVER TRANSMITTER CLOCK INPUT OPTIONS SYNTHESIZERS RF PLLs BB PLL DIGITAL DATA INTERFACE DATA_CLK Signal FB_CLK Signal RX_FRAME Signal ENABLE STATE MACHINE SPI Control Mode Pin Control Mode SPI INTERFACE CONTROL PINS Control Outputs (CTRL_OUT[7:0]) Control Inputs (CTRL_IN[3:0]) GPO PINS (GPO_3 TO GPO_0) AUXILIARY CONVERTERS AUXADC AUXDAC1 and AUXDAC2 POWERING THE AD9361 PACKAGING AND ORDERING INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE