Datasheet ADF4602 (Analog Devices) - 4

制造商Analog Devices
描述Single-Chip, Multiband 3G Femtocell Transceiver
页数 / 页36 / 4 — ADF4602. SPECIFICATIONS. Table 1. Parameter. Min. Typ. Max. Unit. Test …
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ADF4602. SPECIFICATIONS. Table 1. Parameter. Min. Typ. Max. Unit. Test Conditions

ADF4602 SPECIFICATIONS Table 1 Parameter Min Typ Max Unit Test Conditions

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ADF4602 SPECIFICATIONS
VDD = 3.1 V to 3.6 V, GND = 0 V, TA = TMIN to TMAX, unless otherwise noted. Typical specifications are at VDD = 3.3 V and TA = 25°C, 26 MHz reference input level = 0.7 V p-p.
Table 1. Parameter Min Typ Max Unit Test Conditions
REFERENCE SECTION Reference Input Reference Input Frequency 26 MHz Reference Input Amplitude 0.1 0.7 2.0 V p-p Single-ended operation, dc-coupled1 Reference Input Jitter 1.5 ps rms REFCLK Output (26 MHz) Output Load Capacitance 10 40 pF Output Swing 1.5 V p-p 10 pF load Output Slew Rate 200 V/μs 10 pF load Output Duty Cycle Variation 2 % Input duty cycle = 50% Output Jitter 1.5 ps rms CHIPCLK Output (19.2 MHz) Output Load Capacitance 10 40 pF Frequency Multiplication Ratio 48/65 48/65 N/A Output Swing 1.5 V p-p 10 pF load Output Duty Cycle Variation 2 % Input duty cycle = 50% Output Jitter 33 ps rms Lock Time 50 μs TRANSMIT SECTION I/Q Input Input Resistance 100 kΩ Single-ended Input Capacitance 2 pF Single-ended Differential Peak Input Voltage 500 550 mV pd Input Common-Mode Voltage 1.05 1.2 1.4 V Baseband Filter 3 dB Bandwidth 4.0 MHz TX Gain Control Maximum Gain 5 dB 1 V p-p differential baseband input Gain Control Range 60 dB Gain Control Resolution 1/32 dB Average of LSB steps Gain Control Accuracy 1.0 dB Any 1 dB step 10 dB Any 10 dB step Gain Settling Time 1 μs POUT within 0.1 dB of final value RF Specifications (High Band) Carrier Frequency 1710 2170 MHz Output Impedance 50 Ω Output Power (POUT) −8 dBm TM1 signal 64 DPCH Output Noise Spectral Density −155 dBc/Hz 40 MHz offset −161 dBc/Hz 80 MHz offset −161 dBc/Hz 95 MHz offset −163 dBc/Hz 190 MHz offset Carrier Leakage −35 dBc POUT = −8 dBm FDD EVM 5 % POUT = −8 dBm FDD ACLR 55 dB ±5 MHz, POUT = −8 dBm 70 dB ±10 MHz, POUT = −8 dBm Rev. A | Page 4 of 36 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION TRANSMITTER DESCRIPTION I/Q Baseband I/Q Modulator VCO Output TX Output Baluns DACS GENERAL PURPOSE OUTPUTS RECEIVER DESCRIPTION LNAs Mixers Baseband Section Gain Control DC Offset Compensation POWER MANAGEMENT FREQUENCY SYNTHESIS Reference Path SERIAL PORT INTERFACE (SPI) Format OPERATION AND TIMING Read REGISTERS REGISTER MAP REGISTER DESCRIPTION SOFTWARE INITIALIZATION PROCEDURE INITIALIZATION SEQUENCE Nonvolatile Memory (NVM) Initialization Programming Transmit and Receive frequencies APPLICATIONS INFORMATION INTERFACING THE ADF4602 TO THE AD9963 AD9963 ADC Inputs Interfacing to the AD9963 Rx Baseband Inputs AD9963 DAC Outputs Reference Voltage Current Scaling Resistor, RSET Gain Scaling Parameters RECEIVE SENSITIVITY Interfacing to the AD9963 TX Baseband Outputs OUTLINE DIMENSIONS ORDERING GUIDE