Datasheet ADN8833 (Analog Devices) - 9

Data Sheet ADN8833 1.0 20 V V IN = 2.7V AT NO LOAD IN = 3.3V V 0.8 V IN = 3.3V AT NO LOAD IN = 5V VIN = 5.5V AT NO LOAD 15 V %) IN = 2.7V AT 5mA LOAD 0.6 VIN = 3.3V AT 5mA LOAD R ( V 10 IN = 5.5V AT 5mA LOAD 0.4 RRO E %) 5 0.2 R ( NG 0 ADI RRO 0 E RE F –0.2 NT RE –5 V –0.4 –10 –0.6 C CURRE E IT –15 –0.8 –1.0
1 11
–20 –50 0 50 100 150 –1.5 –1.0 –0.5 0
013
AMBIENT TEMPERATURE (°C)
12909-
TEC CURRENT (A)
12909- Figure 10. VREF Error vs. Ambient Temperature Figure 13. ITEC Current Reading Error vs. TEC Current in Cooling Mode
0.20 20 VIN = 3.3V, ITEC = 0A VIN = 3.3V V V IN = 3.3V, ITEC = 0.5A, COOLING IN = 5V 0.15 V 15 IN = 3.3V, ITEC = 0.5A, HEATING %) VIN = 5V, ITEC = 0A R ( 0.10 VIN = 5V, ITEC = 0.5A, COOLING 10 VIN = 5V, ITEC = 0.5A, HEATING RRO E 0.05 5 NG %) ( ADI F 0 0 RE RE V E –0.05 –5 AG LT –0.10 VO –10 EC –0.15 VT –15 –0.20 –20
1
0 1 2 3 4 5 6 7 8 9 10
1 101
0.5 1.0 1.5 2.0 2.5
0
LOAD CURRENT AT VREF (mA)
12909-
TEC VOLTAGE (V)
12909- Figure 11. VREF Load Regulation Figure 14. VTEC Voltage Reading Error vs. TEC Voltage in Cooling Mode
20 20 VIN = 3.3V VIN = 3.3V VIN = 5V VIN = 5V 15 15 %) %) R ( R ( 10 10 RRO RRO E E 5 5 NG NG ADI ADI 0 0 RE RE E NT –5 –5 AG LT –10 VO –10 C CURRE E EC IT –15 VT –15 –20 –20 0 0.5 1.0 1.5
010
–2.5 –2.0 –1.5 –1.0 –0.5
014
TEC CURRENT (A)
12909-
TEC VOLTAGE (V)
12909- Figure 12. ITEC Current Reading Error vs. TEC Current in Heating Mode Figure 15. VTEC Voltage Reading Error vs. TEC Voltage in Heating Mode Rev. B | Page 9 of 23 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS DETAILED FUNCTIONAL BLOCK DIAGRAM THEORY OF OPERATION DIGITAL PID CONTROL POWERING THE DRIVER ENABLE AND SHUTDOWN OSCILLATOR CLOCK FREQUENCY External Clock Operation Connecting Multiple ADN8833 Devices SOFT START ON POWER-UP TEC VOLTAGE/CURRENT MONITOR Voltage Monitor Current Monitor MAXIMUM TEC VOLTAGE LIMIT Using a Resistor Divider to Set the TEC Voltage Limit MAXIMUM TEC CURRENT LIMIT Using a Resistor Divider to Set the TEC Current Limit APPLICATIONS INFORMATION TYPICAL APPLICATION WITH DIGITAL PID USING A DAC THERMISTOR SETUP MOSFET DRIVER AMPLIFIERS PWM OUTPUT FILTER REQUIREMENTS Inductor Selection Capacitor Selection INPUT CAPACITOR SELECTION POWER DISSIPATION PWM Regulator Power Dissipation Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Linear Regulator Power Dissipation PCB LAYOUT GUIDELINES BLOCK DIAGRAMS AND SIGNAL FLOW GUIDELINES FOR REDUCING NOISE AND MINIMIZING POWER LOSS General PCB Layout Guidelines PWM Power Stage Layout Guidelines Linear Power Stage Layout Guidelines EXAMPLE PCB LAYOUT USING TWO LAYERS OUTLINE DIMENSIONS ORDERING GUIDE