Datasheet TLE7272-2E (Infineon) - 7
| 制造商 | Infineon |
| 描述 | 5-V Low Dropout Voltage Regulator |
| 页数 / 页 | 21 / 7 — TLE7272-2. General Product Characteristics. 4.3. Thermal Resistance. … |
| 修订版 | 01_00 |
| 文件格式/大小 | PDF / 441 Kb |
| 文件语言 | 英语 |
TLE7272-2. General Product Characteristics. 4.3. Thermal Resistance. www.jedec.org. Pos. Parameter. Symbol. Limit Values. Unit. Conditions
该数据表的模型线
文件文字版本
link to page 7 link to page 7 link to page 7 link to page 7 link to page 7 link to page 7 link to page 7 link to page 7 link to page 7 link to page 7 link to page 7 link to page 7 link to page 7 link to page 7 link to page 7
TLE7272-2 General Product Characteristics 4.3 Thermal Resistance
Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go to
www.jedec.org
.
Pos. Parameter Symbol Limit Values Unit Conditions Min. Typ. Max. TLE7272-2E (PG-SSOP-14 Exposed Pad)
4.3.1 Junction to Case1) RthJC – 14 – K/W measured to exposed pad 4.3.2 Junction to Ambient1) RthJA – 47 – K/W 2) 4.3.3 RthJA – 141 – K/W footprint only3) 4.3.4 RthJA – 66 – K/W 300 mm² heatsink area3) 4.3.5 RthJA – 56 – K/W 600 mm² heatsink area3)
TLE7272-2D (PG-TO252-5)
4.3.1 Junction to Case1) RthJC – 6 – K/W measured to tab 4.3.2 Junction to Ambient1) RthJA – 32 – K/W 2) 4.3.3 RthJA – 115 – K/W footprint only3) 4.3.4 RthJA – 62 – K/W 300 mm² heatsink area3) 4.3.5 RthJA – 47 – K/W 600 mm² heatsink area3) 1) Not subject to production test, specified by design. 2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer. 3) Specified RthJA value is according to Jedec JESD 51-3 at natural convection on FR4 1s0p board; The Product (Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with 1 copper layer (1 x 70µm Cu). Data Sheet 7 Rev. 1.0, 2009-06-01 Document Outline 1 Overview 2 Block Diagram 3 Pin Configuration 3.1 Pin Assignment PG-SSOP-14 Exposed Pad 3.2 Pin Definitions and Functions PG-SSOP-14 Exposed Pad 3.3 Pin Assignment PG-TO252-5 3.4 Pin Definitions and Functions PG-TO252-5 4 General Product Characteristics 4.1 Absolute Maximum Ratings 4.2 Functional Range 4.3 Thermal Resistance 5 Electrical Characteristics 5.1 Electrical Characteristics Voltage Regulator 5.2 Typical Performance Characteristics Voltage Regulator 5.3 Electrical Characteristics Enable Function 5.4 Typical Performance Characteristics Enable Function 5.5 Electrical Characteristics Reset Function 5.6 Typical Performance Characteristics Reset Function 6 Package Outlines 7 Revision History
TLE7272-2 General Product Characteristics 4.3 Thermal Resistance
Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go to
www.jedec.org
.
Pos. Parameter Symbol Limit Values Unit Conditions Min. Typ. Max. TLE7272-2E (PG-SSOP-14 Exposed Pad)
4.3.1 Junction to Case1) RthJC – 14 – K/W measured to exposed pad 4.3.2 Junction to Ambient1) RthJA – 47 – K/W 2) 4.3.3 RthJA – 141 – K/W footprint only3) 4.3.4 RthJA – 66 – K/W 300 mm² heatsink area3) 4.3.5 RthJA – 56 – K/W 600 mm² heatsink area3)
TLE7272-2D (PG-TO252-5)
4.3.1 Junction to Case1) RthJC – 6 – K/W measured to tab 4.3.2 Junction to Ambient1) RthJA – 32 – K/W 2) 4.3.3 RthJA – 115 – K/W footprint only3) 4.3.4 RthJA – 62 – K/W 300 mm² heatsink area3) 4.3.5 RthJA – 47 – K/W 600 mm² heatsink area3) 1) Not subject to production test, specified by design. 2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer. 3) Specified RthJA value is according to Jedec JESD 51-3 at natural convection on FR4 1s0p board; The Product (Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with 1 copper layer (1 x 70µm Cu). Data Sheet 7 Rev. 1.0, 2009-06-01 Document Outline 1 Overview 2 Block Diagram 3 Pin Configuration 3.1 Pin Assignment PG-SSOP-14 Exposed Pad 3.2 Pin Definitions and Functions PG-SSOP-14 Exposed Pad 3.3 Pin Assignment PG-TO252-5 3.4 Pin Definitions and Functions PG-TO252-5 4 General Product Characteristics 4.1 Absolute Maximum Ratings 4.2 Functional Range 4.3 Thermal Resistance 5 Electrical Characteristics 5.1 Electrical Characteristics Voltage Regulator 5.2 Typical Performance Characteristics Voltage Regulator 5.3 Electrical Characteristics Enable Function 5.4 Typical Performance Characteristics Enable Function 5.5 Electrical Characteristics Reset Function 5.6 Typical Performance Characteristics Reset Function 6 Package Outlines 7 Revision History