Datasheet ADCMP341, ADCMP343 (Analog Devices) - 10

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ADCMP341/ADCMP343 Data Sheet APPLICATION INFORMATION
The ADCMP341/ADCMP343 are dual, low power comparators I >> R3 I BIAS with a built-in 400 mV reference that operates from 1.7 V to 5.5 V. R3 is therefore The comparators are 0.275% accurate with fully programmable hysteresis, implemented using a new technique of a three-resistor V R3 REF = string on the input. These open-drain outputs are capable of IR3 sinking up to 40 mA. Now R2 can be calculated from the following:
COMPARATORS AND INTERNAL REFERENCE
R (V −V ) RISING FALLING R = 3 2 Each of the comparators has one input available externally; the VFALLING other comparator inputs are connected internally to the 400 mV reference. The ADCMP341 has two noninverting comparators R1 can then be calculated using the following equation: and the ADCMP343 has two inverting comparators.   V  1 R = R3 RISING × −1  − R2 There are two input pins available to each comparator. However,    V   REF  these two input pins (±INx_U, ±INx_L) connect to the same input leg of the comparator via a muxing system. This is to where: provide fully programmable rising and falling trip points. The VREF is the specified on chip reference. output of the comparator determines which pin is connected to IBIAS is the maximum specified input bias current. the input of the same comparator. Using Figure 28 as an R1, R2, and R3 are the three resistors as shown in Figure 28. example, when OUTA is high, +INA_U is connected to the IR3 is the current flowing through R3. comparator input. When the input voltage drops and passes VFALLING is the desired falling trip voltage and lower of the two. below the 400 mV reference, the output goes low. This in turn VRISING is the desired rising trip voltage and higher of the two. disconnects +INA_U from the comparator and connects +INA_L. This leg of the string is at a lower voltage and thus
VDD
instantaneously the effect of hysteresis is applied. Therefore, using a resistor string on the input as shown in Figure 28, the
ADCMP341 VINA
voltages for the rising and falling trip points can be programmed
R1 +INA_U
by selecting the appropriate resistors in the string.
R2 UX +INA_L OUTA M POWER SUPPLY R3 400mV
027 The ADCMP341/ADCMP343 are designed to operate from 1.7 V 06500- to 5.5 V. A 0.1 µF decoupling capacitor is recommended between Figure 28. Programming Hysteresis Example VDD and GND.
LAYOUT RECOMMENDATIONS INPUTS
Correct layout is very important to increase noise immunity. The comparator inputs are limited to the maximum VDD voltage Long tracks from the input resistors to the device can lead to range. The voltage on these inputs can be above VDD but never noise being coupled onto the inputs. To avoid this, it is best to above the maximum allowed VDD voltage. place the input resistors as close as possible to the device. It is
OUTPUTS
also recommended that a GND plane is used under this layout. The combination of small hysteresis and the use of a large R3 The open-drain comparator outputs are limited to the maximum resistor further increases susceptibility to noise. In this case, a specified VDD voltage range, regardless of the VDD voltage. These decoupling capacitor (CA, CB) may be required on the ±INx_U outputs are capable of sinking up to 40 mA. Outputs can be tied node to help reduce any noise. A recommended layout example together to provide a common output signal. can be seen in Figure 29.
PROGRAMMING HYSTERESIS GND VDD
When choosing the resistor values, the input bias current must
C1 OUTA OUTB
be considered as a potential source of error. Begin by choosing a
INA INB
resistor value for R3, which takes into account the acceptable
R1A R1B
error introduced by the maximum specified input bias current.
R2A R2B
To reduce this error, the current flowing through the Resistor R3
R3A U1 R3B
should be considerably greater than the input bias current. 028
CA CB
06500- Figure 29. Recommended Layout Example Rev. A | Page 10 of 12 Document Outline Features Applications General Description Functional Block Diagrams Revision History Specifications Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Application Information Comparators and Internal Reference Power Supply Inputs Outputs Programming Hysteresis Layout Recommendations Outline Dimensions Ordering Guide