Datasheet ADCMP606, ADCMP607 (Analog Devices) - 2
| 制造商 | Analog Devices |
| 描述 | Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply CML Comparator in a 12-lead LSCFP Package |
| 页数 / 页 | 14 / 2 — ADCMP606/ADCMP607. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY … |
| 修订版 | C |
| 文件格式/大小 | PDF / 375 Kb |
| 文件语言 | 英语 |
ADCMP606/ADCMP607. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY 4/16—Rev. B to Rev. C. 11/14—Rev. A to Rev. B
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ADCMP606/ADCMP607 Data Sheet TABLE OF CONTENTS
Features .. 1 Applications Information .. 10 Applications ... 1 Power/Ground Layout and Bypassing ... 10 General Description ... 1 CML-Compatible Output Stage ... 10 Functional Block Diagram .. 1 Using/Disabling the Latch Feature ... 10 Revision History ... 2 Optimizing Performance ... 10 Specifications ... 3 Comparator Propagation Delay Dispersion ... 11 Electrical Characteristics ... 3 Comparator Hysteresis .. 11 Timing Information ... 5 Crossover Bias Points ... 12 Absolute Maximum Ratings .. 6 Minimum Input Slew Rate Requirement .. 12 Thermal Resistance .. 6 Typical Application Circuits ... 13 ESD Caution .. 6 Outline Dimensions ... 14 Pin Configurations and Function Descriptions ... 7 Ordering Guide .. 14 Typical Performance Characteristics ... 8
REVISION HISTORY 4/16—Rev. B to Rev. C
Changes to Figure 4 and Table 6 ... 7 Updated Outline Dimensions ... 14 Changes to Ordering Guide .. 14
11/14—Rev. A to Rev. B
Changes to Figure 4 and Table 6 ... 7 Changes to Figure 12 and Figure 13 ... 9 Changes to Comparator Hysteresis Section .. 11 Updated Outline Dimensions ... 14 Changes to Ordering Guide .. 14
8/07—Rev. 0 to Rev. A
Changes to Specifications Section .. 3 Changes to Table 3 .. 6 Changes to Ordering Guide .. 14
10/06—Revision 0: Initial Version
Rev. C | Page 2 of 14 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS TIMING INFORMATION ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION POWER/GROUND LAYOUT AND BYPASSING CML-COMPATIBLE OUTPUT STAGE USING/DISABLING THE LATCH FEATURE OPTIMIZING PERFORMANCE COMPARATOR PROPAGATION DELAY DISPERSION COMPARATOR HYSTERESIS CROSSOVER BIAS POINTS MINIMUM INPUT SLEW RATE REQUIREMENT TYPICAL APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE
ADCMP606/ADCMP607 Data Sheet TABLE OF CONTENTS
Features .. 1 Applications Information .. 10 Applications ... 1 Power/Ground Layout and Bypassing ... 10 General Description ... 1 CML-Compatible Output Stage ... 10 Functional Block Diagram .. 1 Using/Disabling the Latch Feature ... 10 Revision History ... 2 Optimizing Performance ... 10 Specifications ... 3 Comparator Propagation Delay Dispersion ... 11 Electrical Characteristics ... 3 Comparator Hysteresis .. 11 Timing Information ... 5 Crossover Bias Points ... 12 Absolute Maximum Ratings .. 6 Minimum Input Slew Rate Requirement .. 12 Thermal Resistance .. 6 Typical Application Circuits ... 13 ESD Caution .. 6 Outline Dimensions ... 14 Pin Configurations and Function Descriptions ... 7 Ordering Guide .. 14 Typical Performance Characteristics ... 8
REVISION HISTORY 4/16—Rev. B to Rev. C
Changes to Figure 4 and Table 6 ... 7 Updated Outline Dimensions ... 14 Changes to Ordering Guide .. 14
11/14—Rev. A to Rev. B
Changes to Figure 4 and Table 6 ... 7 Changes to Figure 12 and Figure 13 ... 9 Changes to Comparator Hysteresis Section .. 11 Updated Outline Dimensions ... 14 Changes to Ordering Guide .. 14
8/07—Rev. 0 to Rev. A
Changes to Specifications Section .. 3 Changes to Table 3 .. 6 Changes to Ordering Guide .. 14
10/06—Revision 0: Initial Version
Rev. C | Page 2 of 14 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS TIMING INFORMATION ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION POWER/GROUND LAYOUT AND BYPASSING CML-COMPATIBLE OUTPUT STAGE USING/DISABLING THE LATCH FEATURE OPTIMIZING PERFORMANCE COMPARATOR PROPAGATION DELAY DISPERSION COMPARATOR HYSTERESIS CROSSOVER BIAS POINTS MINIMUM INPUT SLEW RATE REQUIREMENT TYPICAL APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE