Datasheet ADCMP606, ADCMP607 (Analog Devices) - 8
制造商 | Analog Devices |
描述 | Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply CML Comparator in a 12-lead LSCFP Package |
页数 / 页 | 14 / 8 — ADCMP606/ADCMP607. Data Sheet. TYPICAL PERFORMANCE CHARACTERISTICS. 800. … |
修订版 | C |
文件格式/大小 | PDF / 375 Kb |
文件语言 | 英语 |
ADCMP606/ADCMP607. Data Sheet. TYPICAL PERFORMANCE CHARACTERISTICS. 800. 250. 600. 200. 400. CC = 2.5V. CC = 5.5V. 150. S (m. ESI ER. –40°C. 100
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文件文字版本
ADCMP606/ADCMP607 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS
VCCI = VCCO = 2.5 V, TA = 25°C, unless otherwise noted.
800 250 600 200 400 V V CC = 2.5V CC = 5.5V V) A) 200 µ 150 ( S (m NT 0 ESI ER –40°C 100 CURRE –200 YST +25°C H –400 50 –600 +125°C –800 0 –1 0 1 2 3 4 5 6 7
026
0 –2 –4 –6 –8 –10 –12 –14 –16 –18
004
LE/HYS PIN (V) LE/HYS PIN CURRENT (µA)
05917- 05917- Figure 5. LE/HYS Pin Current vs. Voltage Figure 8. Hysteresis vs. LE/HYS Pin Current
200 400 150 350 300 100 V V V) A) CC = 2.5V CC = 5.5V 250 µ ( 50 S (m NT ESI 200 0 ER CURRE 150 YST H –50 V 100 CC = 2.5V –100 50 –150 0 –1 0 1 2 3 4 5 6 7
007
50 100 150 200 250 300 350 400 450 500 550 600 650
005
SDN PIN (V) HYS RESISTOR (kΩ)
05917- 05917- Figure 6. SDN Pin Current vs. Voltage Figure 9. Hysteresis vs. Hysteresis Resistor
10 3.5 8 6 3.0 s) n 4 ( AY 2 L 2.5 A) µ 0 N DE ( IO I B –2 AT 2.0 AG P –4 –40°C RO P PROPAGATION DELAY FALL –6 1.5 +25°C –8 +125°C PROPAGATION DELAY RISE –10 1.0 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
006
0 10 20 30 40 50 60 70 80 90 100 110 120 130 140
009
VCM AT VCC = 2.5V OVERDRIVE (mV)
05917- 05917- Figure 7. Input Bias Current vs. Input Common-Mode Voltage Figure 10. Propagation Delay vs. Input Overdrive Rev. C | Page 8 of 14 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS TIMING INFORMATION ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION POWER/GROUND LAYOUT AND BYPASSING CML-COMPATIBLE OUTPUT STAGE USING/DISABLING THE LATCH FEATURE OPTIMIZING PERFORMANCE COMPARATOR PROPAGATION DELAY DISPERSION COMPARATOR HYSTERESIS CROSSOVER BIAS POINTS MINIMUM INPUT SLEW RATE REQUIREMENT TYPICAL APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE