Datasheet ADCMP580, ADCMP581, ADCMP582 (Analog Devices) - 9

制造商Analog Devices
描述Ultrafast SiGe Voltage Comparators
页数 / 页16 / 9 — Data Sheet. ADCMP580/ADCMP581/ADCMP582. TYPICAL PERFORMANCE …
修订版B
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Data Sheet. ADCMP580/ADCMP581/ADCMP582. TYPICAL PERFORMANCE CHARACTERISTICS. VIN COMMON-MODE BIAS SWEEP. A) µ. S (m. ESI. CURRE. YST. 100

Data Sheet ADCMP580/ADCMP581/ADCMP582 TYPICAL PERFORMANCE CHARACTERISTICS VIN COMMON-MODE BIAS SWEEP A) µ S (m ESI CURRE YST 100

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文件文字版本

Data Sheet ADCMP580/ADCMP581/ADCMP582 TYPICAL PERFORMANCE CHARACTERISTICS
VCCI = 5.0 V, VEE = −5.0 V, VCCO = 3.3 V, TA = 25°C, unless otherwise noted.
12 80 70 10 VIN COMMON-MODE BIAS SWEEP 60 A) µ 8 V) ( 50 NT S (m 6 ESI 40 CURRE ER AS 30 4 YST BI H 20 2 10 0 –4 –2 0 2 4 0
006
1 10 100 1k 10k
009
COMMON-MODE (V)
04672-
RHYS CONTROL RESISTOR (Ω)
04672- Figure 5. Bias Current vs. Common-Mode Voltage Figure 8. Hysteresis vs. RHYS Control Resistor
–0.8 2.5 VOH vs. TEMPERATURE –0.9 OUTPUT (NECL) 2.4 V –1.0 OH vs. TEMPERATURE OUTPUT (PECL) 2.3 (V) –1.1 (V) T T PU PU 2.2 T T U –1.2 U O O V 2.1 OL vs. TEMPERATURE –1.3 OUTPUT (NECL) 2.0 –1.4 VOL vs. TEMPERATURE OUTPUT (PECL) –1.5 1.9 –55 –5 45 95 145
007
–55 –5 45 95 145
010
TEMPERATURE (°C) TEMPERATURE (°C)
04672- 04672- Figure 6. ADCMP581 Output Voltage vs. Temperature Figure 9. ADCMP582 Output Voltage vs. Temperature
80 8 +125°C COMMON-MODE OFFSET SWEEP 70 7 60 6 V) 50 V) 5 S (m (m ESI 40 4 SET ER F F O YST 30 3 H +25°C COMMON-MODE OFFSET SWEEP 20 2 –55°C COMMON-MODE OFFSET SWEEP 10 1 0 0 0 100 200 300 400 500 600
008
–2 0 2 4
011
–IHYST (µA) COMMON-MODE (V)
04672- 04672- Figure 7. Hysteresis vs. −IHYST Figure 10. A Typical VOS vs. Common-Mode Voltage Rev. B | Page 9 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING INFORMATION ABSOLUTE MAXIMUM RATINGS THERMAL CONSIDERATIONS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TYPICAL APPLICATION CIRCUITS APPLICATIONS INFORMATION POWER/GROUND LAYOUT AND BYPASSING ADCMP580/ADCMP581/ADCMP582 FAMILY OF OUTPUT STAGES USING/DISABLING THE LATCH FEATURE OPTIMIZING HIGH SPEED PERFORMANCE COMPARATOR PROPAGATION DELAY DISPERSION COMPARATOR HYSTERESIS MINIMUM INPUT SLEW RATE REQUIREMENT OUTLINE DIMENSIONS ORDERING GUIDE NOTES