Datasheet AD8465 (Analog Devices) - 10

AD8465 Data Sheet APPLICATION INFORMATION POWER/GROUND LAYOUT AND BYPASSING LVDS-COMPATIBLE OUTPUT STAGE
The AD8465 comparator is a very high speed device. Despite Specified propagation delay dispersion performance is only the low noise output stage, it is essential to use proper high achieved by keeping parasitic capacitive loads at or below the speed design techniques to achieve the specified performance. specified minimums. The outputs of the AD8465 are designed Because the comparator is an uncompensated amplifier, feedback to directly drive any standard LVDS-compatible input. in any phase relationship is likely to cause oscil ations or undesired
USING/DISABLING THE LATCH FEATURE
hysteresis. The use of low impedance supply planes is of critical importance particularly with the output supply plane (V The latch input is designed for maximum versatility. It can CCO) and the ground plane (GND). Individual supply planes are safely be left floating or it can be driven low by any standard recommended as part of a multilayer board. Providing the TTL/CMOS device as a high speed latch. In addition, the pin lowest inductance return path for switching currents ensures can be operated as a hysteresis control pin with a bias voltage the best possible performance in the target application. of 1.25 V nominal and an input resistance of approximately 70 kΩ. This allows the comparator hysteresis to be easily It is also important to adequately bypass the input and output controlled by either a resistor or an inexpensive CMOS DAC. supplies. Place multiple high quality 0.01 µF bypass capacitors Driving this pin high or floating the pin disables all hysteresis. as close as possible to each of the VCCI and VCCO supply pins and connect the capacitors to the GND plane with redundant vias. Hysteresis control and latch mode can be used together if an Place at least one capacitor to provide a physical y short return open drain, an open collector, or a three-state driver is connected path for output currents flowing back from ground to the V in parallel to the hysteresis control resistor or current source. CCI pin and the VCCO pin. Carefully select high frequency bypass Due to the programmable hysteresis feature, the logic threshold capacitors for minimum inductance and ESR. Parasitic layout of the latch pin is approximately 1.1 V, regardless of VCCO. inductance should also be strictly control ed to maximize the
OPTIMIZING PERFORMANCE
effectiveness of the bypass at high frequencies. As with any high speed comparator, proper design and layout The input and output supplies have been connected separately techniques are essential for obtaining the specified performance. (VCCI ≠ VCCO); be sure to bypass each of these supplies separately Stray capacitance, inductance, inductive power and ground imped- to the GND plane. Do not connect a bypass capacitor between ances, or other layout issues can severely limit performance and these supplies. It is recommended that the GND plane separate often cause oscillation. Large discontinuities along input and the VCCI and VCCO planes when the circuit board layout is designed output transmission lines can also limit the specified pulse width to minimize coupling between the two supplies to take advan- dispersion performance. Minimize the source impedance as tage of the additional bypass capacitance from each respective much as is practicable. High source impedance, in combina- supply to the ground plane. This enhances the performance when tion with the parasitic input capacitance of the comparator, split input/output supplies are used. If the input and output supplies causes an undesirable degradation in bandwidth at the input, are connected together for single-supply operation (VCCI = VCCO), thus degrading the overal response. Thermal noise from large coupling between the two supplies is unavoidable; however, resistances can easily cause extra jitter with slowly slewing input careful board placement can help keep output return currents signals. Higher impedances encourage undesired coupling. away from the inputs. Rev. B | Page 10 of 14 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS TIMING INFORMATION ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATION INFORMATION POWER/GROUND LAYOUT AND BYPASSING LVDS-COMPATIBLE OUTPUT STAGE USING/DISABLING THE LATCH FEATURE OPTIMIZING PERFORMANCE COMPARATOR PROPAGATION DELAY DISPERSION COMPARATOR HYSTERESIS CROSSOVER BIAS POINTS MINIMUM INPUT SLEW RATE REQUIREMENT TYPICAL APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE AUTOMOTIVE PRODUCTS