Datasheet HMC675LC3C (Analog Devices) - 4
| 制造商 | Analog Devices |
| 描述 | 10 GHz Latched Comparator with RSCML Output Stage |
| 页数 / 页 | 10 / 4 — HMC675LC3C. 10 GHz LATCHED COMPARATOR. WITH RSCML OUTPUT STAGE. Timing … |
| 文件格式/大小 | PDF / 569 Kb |
| 文件语言 | 英语 |
HMC675LC3C. 10 GHz LATCHED COMPARATOR. WITH RSCML OUTPUT STAGE. Timing Diagram
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HMC675LC3C
v10.0514
10 GHz LATCHED COMPARATOR WITH RSCML OUTPUT STAGE Timing Diagram
T M S - S R O AT R A P OM C Symbol Timing Description Propagation delay measured from the time the input signal crosses the reference tPDH Input to output high delay (± the input offset voltage) to the 50% point of an output low-to-high transition. Propagation delay measured from the time the input signal crosses the reference tPDL Input to output low delay (± the input offset voltage) to the 50% point of an output high-to-low transition. Propagation delay measured from the 50% point of the latch enable signal high-to-low tPLOH Latch enable to output high delay transition to the 50% point of an output low-to-high transition. Propagation delay measured from the 50% point of the latch enable signal high-to-low tPLOL Latch enable to output low delay transition to the 50% point of an output high-to-low transition. Minimum time after the positive transition of the latch enable signal that the input signal tH Minimum hold time must remain unchanged to be acquired and held at the outputs. Minimum time that the latch enable signal must be low to acquire an input signal tPL Minimum latch enable pulse width change. Minimum time before the positive transition of the latch enable signal that an input tS Minimum setup time signal change must be present to be acquired and held at the outputs. Amount of time required to transition from a low to a high output as measured at the tR Output rise time 20% and 80% points. Amount of time required to transition from a high to a low output as measured at the tF Output fall time 20% and 80% points. VOD Voltage overdrive Difference between the input voltages VINP and VINN- I F nf o or r p mati r o in cfe ur , d nish e e l d iv b e y r A y a nalo n g d t Devi o p ces i la s c bele o ieve rd d t e o rbs e : H acc iutrtatite e M and ic reli rao bl w e. a H v o e C wever o , nrp o For price, delivery, and to place orders: Analog Devices, Inc., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other oration, 2 Elizabeth Drive, Chelmsford, MA 01824 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 Phone: 978-250-3343 Fax: 978-250-3373 O rights of third parties that may result from its use. Specifications subject to change without notice. No rd Phoe n r O e: 7 n- 81-li 3 n 2 e a 9-4 t w 70 ww 0 • O . rdh e itt r o it nle i . n co e a m license is granted by implication or otherwise under any patent or patent rights of Analog Devices. t www.analog.com
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Application Support: Phon Trademarks and registered trademarks are the property of their respective owners. e: 978-250-334 A 3 o pplic r a atio pp n S s u @ p h por ittti : Pte ho.c n o e m : 1-800-ANALOG-D
v10.0514
10 GHz LATCHED COMPARATOR WITH RSCML OUTPUT STAGE Timing Diagram
T M S - S R O AT R A P OM C Symbol Timing Description Propagation delay measured from the time the input signal crosses the reference tPDH Input to output high delay (± the input offset voltage) to the 50% point of an output low-to-high transition. Propagation delay measured from the time the input signal crosses the reference tPDL Input to output low delay (± the input offset voltage) to the 50% point of an output high-to-low transition. Propagation delay measured from the 50% point of the latch enable signal high-to-low tPLOH Latch enable to output high delay transition to the 50% point of an output low-to-high transition. Propagation delay measured from the 50% point of the latch enable signal high-to-low tPLOL Latch enable to output low delay transition to the 50% point of an output high-to-low transition. Minimum time after the positive transition of the latch enable signal that the input signal tH Minimum hold time must remain unchanged to be acquired and held at the outputs. Minimum time that the latch enable signal must be low to acquire an input signal tPL Minimum latch enable pulse width change. Minimum time before the positive transition of the latch enable signal that an input tS Minimum setup time signal change must be present to be acquired and held at the outputs. Amount of time required to transition from a low to a high output as measured at the tR Output rise time 20% and 80% points. Amount of time required to transition from a high to a low output as measured at the tF Output fall time 20% and 80% points. VOD Voltage overdrive Difference between the input voltages VINP and VINN- I F nf o or r p mati r o in cfe ur , d nish e e l d iv b e y r A y a nalo n g d t Devi o p ces i la s c bele o ieve rd d t e o rbs e : H acc iutrtatite e M and ic reli rao bl w e. a H v o e C wever o , nrp o For price, delivery, and to place orders: Analog Devices, Inc., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other oration, 2 Elizabeth Drive, Chelmsford, MA 01824 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 Phone: 978-250-3343 Fax: 978-250-3373 O rights of third parties that may result from its use. Specifications subject to change without notice. No rd Phoe n r O e: 7 n- 81-li 3 n 2 e a 9-4 t w 70 ww 0 • O . rdh e itt r o it nle i . n co e a m license is granted by implication or otherwise under any patent or patent rights of Analog Devices. t www.analog.com
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Application Support: Phon Trademarks and registered trademarks are the property of their respective owners. e: 978-250-334 A 3 o pplic r a atio pp n S s u @ p h por ittti : Pte ho.c n o e m : 1-800-ANALOG-D