Datasheet HMC674LC3C, HMC674LP3E (Analog Devices)

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9.3 GHz Latched Comparator with RSPECL Output Stage Data Sheet HMC674LC3C /HMC674LP3E FEATURES FUNCTIONAL BLOCK DIAGRAM Equivalent input bandwidth: 9.3 GHz typical HMC674LC3C/HMC674LP3E Propagation delay: 85 ps typical N S CCI EE V RT HY V Overdrive and slew rate dispersion: 10 ps typical 16 15 14 13 Input signal minimum pulse width: 60 ps typical VTP 1 12 VCCO Resistor programmable hysteresis INP 2 50Ω 11 Q Differential latch control INN 3 10 50Ω Q Power dissipation: 140 mW typical VTN 4 9 16-terminal, 3 mm × 3 mm, ceramic leadless chip carrier (LCC) VCCO 16-lead lead frame chip scale package (LFCSP) 5 6 7 8 C PACKAGE CCI LE LE BASE V NI
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V APPLICATIONS EE
14861- Figure 1. HMC674LC3C/HMC674LP3E Functional Block Diagram
Automatic test equipment (ATE) applications High speed instrumentation Digital receiver systems Pulse spectroscopy High speed trigger circuits Clock and data restoration GENERAL DESCRIPTION
The HMC674LC3C/HMC674LP3E are silicon germanium applications from ATE to broadband communications. The (SiGe), monolithic, ultrafast comparators that feature reduced RSPECL output stages directly drive 400 mV into a 50 Ω resistor swing positive emitter-coupled logic (RSPECL) output drivers terminated to VTT = (VCCO − 2.0 V), where VTT is the PECL and latch inputs. These comparators support 10 Gbps operation termination voltage (see Figure 16). The HMC674LC3C/ and provide 85 ps propagation delay and an input signal HMC674LP3E feature a high speed latch and programmable minimum pulse width of 60 ps with 0.2 ps rms of random jitter hysteresis. These devices can operate in either latch mode or as (RJ). Overdrive and slew rate dispersion is typically 10 ps, making a tracking comparator. the HMC674LC3C/HMC674LP3E ideal for a wide range of
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Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS LATCH ENABLE (LE/) SPECIFICATIONS DC OUTPUT SPECIFICATIONS AC SPECIFICATIONS POWER SUPPLY SPECIFICATIONS TIMING DESCRIPTIONS Timing Diagram ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION POWER SEQUENCING APPLICATIONS INFORMATION EVALUATION PRINTED CIRCUIT BOARD (PCB) APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE