Datasheet LT1016 (Analog Devices) - 6

LT1016
APPLICATIONS INFORMATION Common Mode Considerations
Input capacitance is typically 3.5pF. This is measured by The LT1016 is specified for a common mode range of inserting a 1k resistor in series with the input and measur- –3.75V to 3.5V with supply voltages of ±5V. A more ing the resultant change in propagation delay. general consideration is that the common mode range
LATCH Pin Dynamics
is 1.25V above the negative supply and 1.5V below the positive supply, independent of the actual supply voltage. The LATCH pin is intended to retain input data (output The criteria for common mode limit is that the output still latched) when the LATCH pin goes high. This pin will responds correctly to a small differential input signal. float to a high state when disconnected, so a flowthrough Either input may be outside the common mode limit (up condition requires that the LATCH pin be grounded. To to the supply voltage) as long as the remaining input is guarantee data retention, the input signal must be valid at within the specified limit, and the output will still respond least 5ns before the latch goes high (setup time) and must correctly. There is one consideration, however, for inputs remain valid at least 3ns after the latch goes high (hold that exceed the positive common mode limit. Propagation time). When the latch goes low, new data will appear at delay will be increased by up to 10ns if the signal input the output in approximately 8ns to 10ns. The LATCH pin is more positive than the upper common mode limit and is designed to be driven with TTL or CMOS gates. It has then switches back to within the common mode range. no built-in hysteresis. This effect is not seen for signals more negative than the lower common mode limit.
Measuring Response Time
The LT1016 is able to respond quickly to fast low level
Input Impedance and Bias Current
signals because it has a very high gain-bandwidth prod- Input bias current is measured with the output held at uct (≈50GHz), even at very high frequencies. To properly 1.4V. As with any simple NPN differential input stage, the measure the response of the LT1016 requires an input LT1016 bias current will go to zero on an input that is low signal source with very fast rise times and exceptionally and double on an input that is high. If both inputs are less clean settling characteristics. This last requirement comes than 0.8V above V–, both input bias currents will go to about because the standard comparator test calls for an zero. If either input exceeds the positive common mode input step size that is large compared to the overdrive limit, input bias current will increase rapidly, approaching amplitude. Typical test conditions are 100mV step size several milliamperes at VIN = V+. with only 5mV overdrive. This requires an input signal that settles to within 1% (1mV) of final value in only a few Differential input resistance at zero differential input nanoseconds with no ringing or “long tailing.” Ordinary voltage is about 10kΩ, rapidly increasing as larger DC high speed pulse generators are not capable of generating differential input signals are applied. Common mode such a signal, and in any case, no ordinary oscilloscope input resistance is about 4MΩ with zero differential input is capable of displaying the waveform to check its fidelity. voltage. With large differential input signals, the high input Some means must be used to inherently generate a fast, will have an input resistance of about 2MΩ and the low clean edge with known final value. input greater than 20MΩ. Rev D 6 For more information www.analog.com Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Applications Information Typical Applications Appendix A Package Description Revision History Applications Information Related Parts