Datasheet ADP7158 (Analog Devices) - 6

ADP7158 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VOUT 1 10 VIN VOUT 2 9 VIN ADP7158 VOUT 1 8 VIN VOUT_SENSE 3 8 VREG TOP VIEW VOUT_SENSE 2 ADP7158 7 VREG BYP 4 (Not to Scale) 7 REF TOP VIEW BYP 3 (Not to Scale) 6 REF EN 5 6 REF_SENSE EN 4 5 REF_SENSE NOTES NOTES 1. THE EXPOSED PAD IS LOCATED ON THE BOTTOM OF 1. THE EXPOSED PAD IS LOCATED ON THE BOTTOM OF THE PACKAGE. THE EXPOSED PAD ENHANCES THERMAL THE PACKAGE. THE EXPOSED PAD ENHANCES THERMAL PERFORMACE, AND IT IS ELECTRICALLY CONNECTED TO PERFORMACE, AND IT IS ELECTRICALLY CONNECTED TO GROUND INSIDE THE PACKAGE. CONNECT THE EXPOSED GROUND INSIDE THE PACKAGE. CONNECT THE EXPOSED
003 4
PAD TO THE GROUND PLANE ON THE BOARD TO ENSURE
6-
PAD TO THE GROUND PLANE ON THE BOARD TO ENSURE
00 6-
PROPER OPERATION.
1289
PROPER OPERATION.
289 1 Figure 3. 10-Lead LFCSP Pin Configuration Figure 4. 8-Lead SOIC Pin Configuration
Table 6. Pin Function Descriptions Pin No. LFCSP SOIC Mnemonic Description
1, 2 1 VOUT Regulated Output Voltage. Bypass VOUT to ground with a 10 μF or greater capacitor. 3 2 VOUT_SENSE Output Sense. VOUT_SENSE is internally connected to VOUT with a 10 Ω resistor. Connect VOUT_SENSE as close to the load as possible. 4 3 BYP Low Noise Bypass Capacitor. Connect a 1 μF capacitor from the BYP pin to ground to reduce noise. Do not connect a load to this pin. 5 4 EN Enable. Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For automatic startup, connect EN to VIN. 6 5 REF_SENSE Reference Sense. Connect REF_SENSE to the REF pin. Do not connect REF_SENSE to VOUT or ground. 7 6 REF Low Noise Reference Voltage Output. Bypass REF to ground with a 1 μF or greater capacitor. Short REF_SENSE to REF for fixed output voltages. Do not connect a load to this pin. 8 7 VREG Regulated Input Supply Voltage to Low Dropout (LDO) Amplifier. Bypass VREG to ground with a 1 μF or greater capacitor. 9, 10 8 VIN Regulator Input Supply Voltage. Bypass VIN to ground with a 10 μF or greater capacitor. EPAD Exposed Pad. The exposed pad is located on the bottom of the package. The exposed pad enhances thermal performance, and it is electrically connected to ground inside the package. Connect the exposed pad to the ground plane on the board to ensure proper operation. Rev. C | Page 6 of 22 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TYPICAL APPLICATION CIRCUIT TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS INPUT AND OUTPUT CAPACITORS, RECOMMENDED SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL DATA THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION ADIsimPower DESIGN TOOL CAPACITOR SELECTION Output Capacitor Input and VREG Capacitor REF Capacitor BYP Capacitor Capacitor Properties UVLO PROGRAMMABLE PRECISION ENABLE START-UP TIME REF, BYP, AND VREG PINS CURRENT LIMIT AND THERMAL SHUTDOWN THERMAL CONSIDERATIONS Thermal Characterization Parameter (ΨJB) PCB LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE