Datasheet ADP7156 (Analog Devices) - 4

制造商Analog Devices
描述1.2 A, Ultralow Noise, High PSRR, Fixed Output, RF Linear Regulator
页数 / 页22 / 4 — ADP7156. Data Sheet. Parameter. Symbol. Test Conditions/Comments. Min. …
修订版B
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ADP7156. Data Sheet. Parameter. Symbol. Test Conditions/Comments. Min. Typ. Max. Unit

ADP7156 Data Sheet Parameter Symbol Test Conditions/Comments Min Typ Max Unit

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ADP7156 Data Sheet Parameter Symbol Test Conditions/Comments Min Typ Max Unit
VREG UVLO THRESHOLDS7 Rising VREGUVLORISE 1.94 V Falling VREGUVLOFALL 1.60 V Hysteresis VREGUVLOHYS 185 mV EN INPUT PRECISION 2.3 V ≤ VIN ≤ 5.5 V EN Input Logic High VEN_HIGH 1.13 1.22 1.31 V Logic Low VEN_LOW 1.05 1.13 1.22 V Logic Hysteresis VEN_HYS 90 mV LEAKAGE CURRENT REF_SENSE IREF_SENSE_LKG 10 nA EN IEN_LKG EN = VIN or GND 0.01 1 µA 1 Guaranteed by characterization; not production tested. 2 The ADP7156 is available in 16 standard voltages between 1.2 V and 3.3 V, including 1.2 V, 1.3 V, 1.5 V, 1.6 V, 1.8 V, 2.0 V, 2.2 V, 2.5 V, 2.6 V, 2.7 V, 2.8 V, 2.9 V, 3.0 V, 3.1 V, 3.2 V, and 3.3 V. 3 Based on an endpoint calculation using 10 mA and 1.2 A loads. 4 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V. 5 Dropout voltage is defined as the input to output voltage differential when the input voltage is set to the nominal output voltage. Dropout voltage applies only for output voltages greater than 2.3 V. 6 Start-up time is defined as the time between the rising edge of VEN to VOUT, VREG, or VREF being at 90% of its nominal value. 7 The output voltage is disabled until the VREG UVLO rise threshold is crossed. The VREG output is disabled until the input voltage UVLO rising threshold is crossed.
INPUT AND OUTPUT CAPACITORS, RECOMMENDED SPECIFICATIONS Table 3. Parameter Symbol Test Conditions/Comments Min Typ Max Unit
MINIMUM CAPACITANCE TA = −40°C to +125°C Input1 CIN 7.0 10.0 µF Regulator CREG 0.7 1.0 µF Output1 COUT 7.0 10.0 µF Bypass CBYP 0.1 1.0 µF Reference CREF 0.7 1.0 µF CAPACITOR EFFECTIVE SERIES RESISTANCE (ESR) TA = −40°C to +125°C COUT, CIN RESR 0.1 Ω CREG, CREF RESR 0.2 Ω CBYP RESR 2.0 Ω 1 The minimum input and output capacitance must be greater than 7.0 μF over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended; Y5V and Z5U capacitors are not recommended for use with any low dropout regulator. Rev. B | Page 4 of 22 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TYPICAL APPLICATION CIRCUIT REVISION HISTORY SPECIFICATIONS INPUT AND OUTPUT CAPACITORS, RECOMMENDED SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL DATA THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION ADIsimPOWER DESIGN TOOL CAPACITOR SELECTION Output Capacitor Input and VREG Capacitor REF Capacitor BYP Capacitor Capacitor Properties UNDERVOLTAGE LOCKOUT (UVLO) PROGRAMMABLE PRECISION ENABLE START-UP TIME REF, BYP, AND VREG PINS CURRENT-LIMIT AND THERMAL SHUTDOWN THERMAL CONSIDERATIONS Thermal Characterization Parameter (ΨJB) PRINTED CIRCUIT BOARD (PCB) LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE