Datasheet ADP7112 (Analog Devices) - 3

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Data Sheet ADP7112 SPECIFICATIONS
VIN = VOUT + 1 V or 2.7 V, whichever is greater, VOUT = 5 V, EN = VIN, IOUT = 10 mA, CIN = COUT = 2.2 μF, CSS = 0 pF, TA = 25°C for typical specifications, TJ = −40°C to +125°C for minimum/maximum specifications, unless otherwise noted.
Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT VOLTAGE RANGE VIN 2.7 20 V MAXIMUM OUTPUT CURRENT ILOAD_MAX 200 mA OPERATING SUPPLY CURRENT IGND IOUT = 0 μA 50 140 μA IOUT = 10 mA 80 190 μA IOUT = 200 mA 180 320 μA SHUTDOWN CURRENT IGND-SD EN = GND 1.8 μA EN = GND, VIN = 20 V 3.0 10 μA OUTPUT VOLTAGE ACCURACY Output Voltage Accuracy VOUT IOUT = 10 mA, TJ = 25°C –0.8 +0.8 % 100 μA < IOUT < 200 mA, VIN = (VOUT + 1 V) to 20 V –1.8 +1.8 % LINE REGULATION ∆VOUT/∆VIN VIN = (VOUT + 1 V) to 20 V –0.02 +0.02 %/V LOAD REGULATION1 ∆VOUT/∆IOUT IOUT = 100 μA to 200 mA 0.002 0.004 %/mA SENSE INPUT BIAS CURRENT SENSEI-BIAS 100 μA < IOUT < 200 mA VIN = (VOUT + 1 V) to 20 V 10 1000 nA DROPOUT VOLTAGE2 VDROPOUT IOUT = 10 mA 30 60 mV IOUT = 200 mA 200 420 mV START-UP TIME3 TSTART-UP VOUT = 5 V 380 μs SOFT START SOURCE CURRENT SSI-SOURCE SS = GND 1.15 μA CURRENT-LIMIT THRESHOLD4 ILIMIT 250 360 460 mA THERMAL SHUTDOWN Thermal Shutdown Threshold TSSD TJ rising 150 °C Thermal Shutdown Hysteresis TSSD-HYS 15 °C UNDERVOLTAGE THRESHOLDS Input Voltage Rising UVLORISE 2.69 V Input Voltage Falling UVLOFALL 2.2 V Hysteresis UVLOHYS 230 mV EN INPUT STANDBY 2.7 V ≤ VIN ≤ 20 V EN Input Logic High ENSTBY-HIGH 1.0 V EN Input Logic Low ENSTBY-LOW 0.4 V EN Input Logic Hysteresis ENSTBY-HYS 150 mV EN INPUT PRECISION 2.7 V ≤ VIN ≤ 20 V EN Input Logic High ENHIGH 1.15 1.22 1.30 V EN Input Logic Low ENLOW 1.06 1.12 1.18 V EN Input Logic Hysteresis ENHYS 100 mV EN Input Leakage Current IEN-LKG EN = VIN or GND 0.04 1 μA EN Input Delay Time tEN-DLY From EN rising from 0 V to VIN to 0.1 × VOUT 80 μs OUTPUT NOISE OUTNOISE 10 Hz to 100 kHz, all output voltage options 11 μV rms POWER SUPPLY REJECTION RATIO PSRR 1 MHz, VIN = 7 V, VOUT = 5 V 50 dB 100 kHz, VIN = 7 V, VOUT = 5 V 68 dB 10 kHz, VIN = 7 V, VOUT = 5 V 88 dB 1 Based on an endpoint calculation using 100 μA and 200 mA loads. See Figure 5 for typical load regulation performance for loads less than 1 mA. 2 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. Dropout applies only for output voltages greater than 2.7 V. 3 Start-up time is defined as the time between the rising edge of EN to VOUT being at 90% of its nominal value. 4 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 5.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of 5.0 V or 4.5 V. Rev. D | Page 3 of 21 Document Outline Features Applications Typical Application Circuits General Description Revision History Specifications Input and Output Capacitance, Recommended Specifications Absolute Maximum Ratings Thermal Data Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Applications Information Capacitor Selection Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties Programable Precision Enable Soft Start Noise Reduction of the ADP7112 in Adjustable Mode Current-Limit and Thermal Overload Protection Effect of Noise Reduction on Start-Up Time Thermal Considerations PCB Layout Considerations Outline Dimensions Ordering Guide