Datasheet ADM7155 (Analog Devices) - 5

Data Sheet ADM7155 ABSOLUTE MAXIMUM RATINGS Table 4.
Junction-to-ambient thermal resistance (θJA) of the package is based on modeling and calculation using a 4-layer PCB. The
Parameter Rating
junction-to-ambient thermal resistance is highly dependent on VIN to GND −0.3 V to +7 V the application and PCB layout. In applications where high VREG to GND −0.3 V to VIN, or +4 V (whichever is less) maximum power dissipation exists, close attention to thermal VOUT to GND −0.3 V to VREG, or +4 V PCB design is required. The value of θJA may vary, depending (whichever is less) on PCB material, layout, and environmental conditions. The BYP to VOUT ±0.3 V specified values of θJA are based on a 4-layer, 4 in. × 3 in. circuit EN to GND −0.3 V to +7 V board. See JESD51-7 and JESD51-9 for detailed information on BYP to GND −0.3 V to VREG, or +4 V the board construction. (whichever is less) ΨJB is the junction-to-board thermal characterization parameter REF to GND −0.3 V to VREG, or +4 V with units of °C/W. ΨJB of the package is based on modeling and (whichever is less) calculation using a 4-layer PCB. JESD51-12, Guidelines for REF_SENSE to GND −0.3 V to +4 V Reporting and Using Electronic Package Thermal Information, Storage Temperature Range −65°C to +150°C states that thermal characterization parameters are not the same Junction Temperature 150°C as thermal resistances. ΨJB measures the component power Operating Ambient Temperature −40°C to +125°C Range flowing through multiple thermal paths rather than a single Soldering Conditions JEDEC J-STD-020 path as in thermal resistance, θJB. Therefore, ΨJB thermal paths include convection from the top of the package as well as radiation from the package, factors that make Ψ Stresses at or above those listed under Absolute Maximum JB more useful in real-world applications. Maximum junction temperature (T Ratings may cause permanent damage to the product. This is a J) is calculated from the PCB temperature (T stress rating only; functional operation of the product at these B) and power dissipation (P or any other conditions above those indicated in the operational D) using the formula section of this specification is not implied. Operation beyond TJ = TB + (PD × ΨJB) the maximum operating conditions for extended periods may See JESD51-8 and JESD51-12 for more detailed information affect product reliability. about ΨJB.
THERMAL DATA THERMAL RESISTANCE
Absolute maximum ratings apply individually only, not in θJA, θJC, and ΨJB are specified for the worst case conditions, that combination. The ADM7155 can be damaged when the is, a device soldered in a circuit board for surface-mount junction temperature limits are exceeded. Monitoring ambient packages. temperature does not guarantee that TJ is within the specified temperature limits. In applications with high power dissipation
Table 5. Thermal Resistance
and poor thermal resistance, the maximum ambient temper-
Package Type θJA θJC ΨJB Unit
ature may need to be derated. 8-Lead LFCSP 36.7 23.5 13.3 °C/W In applications with moderate power dissipation and low 8-Lead SOIC 36.9 27.1 18.6 °C/W printed circuit board (PCB) thermal resistance, the maximum ambient temperature can exceed the maximum limit provided
ESD CAUTION
that the junction temperature is within specification limits. The junction temperature (TJ) of the device is dependent on the ambient temperature (TA), the power dissipation of the device (PD), and the junction-to-ambient thermal resistance of the package (θJA). Maximum junction temperature (TJ) is calculated from the ambient temperature (TA) and power dissipation (PD) using the following formula: TJ = TA + (PD × θJA) Rev. C | Page 5 of 24 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUIT GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL DATA THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION ADIsimPOWER DESIGN TOOL CAPACITOR SELECTION Output Capacitor Input and VREG Capacitor REF Capacitor BYP Capacitor Capacitor Properties UNDERVOLTAGE LOCKOUT (UVLO) PROGRAMMABLE PRECISION ENABLE START-UP TIME REF, BYP, AND VREG PINS CURRENT-LIMIT AND THERMAL OVERLOAD PROTECTION THERMAL CONSIDERATIONS Thermal Characterization Parameter (ΨJB) PSRR PERFORMANCE PCB LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE