Datasheet HMC1060LP3E (Analog Devices) - 9

HMC1060LP3E
v00.1211
QUAD LOW NOISE HIGH PSRR LINEAR VOLTAGE REGULATOR Application Schematic
t M g - S in n io it d n o r C e w o P in order to achieve the typical noise performance specified in the electrical Specifications table, a 4.7 µF decoupling capacitor between reF and gnd pins (C1), and 100 nF capacitors connected between output pins Vrx (x=1,2,3,4) and respective rdx pins (C2, C3, C4 and C5) are required. if noise performance is not critical for a particular output, the 100 nF capacitor can be omitted for the corresponding regulator output. in that case, noise spectral density will typical y increase by a factor of 20 at 10 kHz. the 4.7 µF reF capacitor causes approximately 40 ms typical turn-on start-up time. the effects of reducing the reF capacitor on regulator noise performance and regulator turn-on time are shown in Figure 2 and external enable Pin & Power Up timing section respectively. Inf F or o m r p atio r n ifc ur e n , d ishe e d lbiv y e A r n y a alog n D d t evic o p es is la beclie o eved rd to ebre sa: H ccur iattti e tae M nd re ilicarbloew . H a o ve C wever, o n rp o For price, delivery, and to place orders: Analog Devices, Inc., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other oration, 2 Elizabeth Drive, Chelmsford, MA 01824 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 Phone: 978-250-3343 Fax: 978-250-3373 O rights of third parties that may result from its use. Specifications subject to change without notice. No P rd ho e ne r O : 7 n 81- -3li 2n 9 e a -47 t w 0 w 0 • O w rd .h e it r o tniltie n .c e ao t m
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