Datasheet ADP320 (Analog Devices) - 5

Data Sheet ADP320 ABSOLUTE MAXIMUM RATINGS Table 3.
Junction-to-ambient thermal resistance (θJA) of the package is
Parameter Rating
based on modeling and calculation using a 4-layer board. The junction-to-ambient thermal resistance is highly dependent on VIN1/VIN2, VIN3, VBIAS to GND –0.3 V to +6.5 V the application and board layout. In applications where high VOUT1, VOUT2 to GND –0.3 V to VIN1/VIN2 maximum power dissipation exists, close attention to thermal VOUT3 to GND –0.3 V to VIN3 board design is required. The value of θ EN1, EN2, EN3 to GND –0.3 V to +6.5 V JA may vary, depending on PCB material, layout, and environmental conditions. The Storage Temperature Range –65°C to +150°C specified values of θ Operating Junction Temperature Range –40°C to +125°C JA are based on a four-layer, 4-inch × 3-inch circuit board. Refer to JEDEC JESD 51-9 for detailed informa- Soldering Conditions JEDEC J-STD-020 tion on the board construction. For additional information, see Stresses at or above those listed under Absolute Maximum the AN-617 Application Note, MicroCSP™ Wafer Level Chip Ratings may cause permanent damage to the product. This is a Scale Package. stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational ΨJB is the junction to board thermal characterization parameter section of this specification is not implied. Operation beyond with units of °C/W. ΨJB of the package is based on modeling and the maximum operating conditions for extended periods may calculation using a 4-layer board. The JESD51-12, Guidelines for affect product reliability. Reporting and Using Package Thermal Information, states that thermal characterization parameters are not the same as
THERMAL DATA
thermal resistances. ΨJB measures the component power flowing Absolute maximum ratings apply individually only, not in through multiple thermal paths rather than a single path as in combination. thermal resistance, θJB. Therefore, ΨJB thermal paths include convection from the top of the package as well as radiation from The ADP320 triple LDO can be damaged when the junction the package; factors that make Ψ temperature limits are exceeded. Monitoring ambient temper- JB more useful in real-world applications. Maximum junction temperature (T ature does not guarantee that the junction temperature (T J) is calculated J) is from the board temperature (T within the specified temperature limits. In applications with B) and power dissipation (PD) using the following formula high power dissipation and poor thermal resistance the maximum ambient temperature may have to be derated. In TJ = TB + (PD × ΨJB) applications with moderate power dissipation and low PCB Refer to JEDEC JESD51-8 and JESD51-12 for more detailed thermal resistance, the maximum ambient temperature can information about ΨJB. exceed the maximum limit as long as the junction temperature is within specification limits.
THERMAL RESISTANCE
The junction temperature (TJ) of the device is dependent on the θJA and ΨJB are specified for the worst-case conditions, that is, a ambient temperature (TA), the power dissipation of the device device soldered in a circuit board for surface-mount packages. (PD), and the junction-to-ambient thermal resistance of the package (θ
Table 4.
JA). Maximum junction temperature (TJ) is calculated from the ambient temperature (TA) and power dissi-pation (PD)
Package Type θJA ΨJB Unit
using the following formula: 16-Lead 3 mm × 3 mm LFCSP 49.5 25.2 °C/W TJ = TA + (PD × θJA)
ESD CAUTION
Rev. C | Page 5 of 21 Document Outline Features Applications Typical Application Circuits General Description Revision History Specifications Input and Output Capacitor, Recommended Specifications Absolute Maximum Ratings THERMAL DATA Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Theory of Operation Applications Information ADIsimPower Design Tool Capacitor Selection Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties Undervoltage Lockout Enable Feature Current-Limit and Thermal Overload Protection Thermal Considerations Printed Circuit Board Layout Considerations Outline Dimensions Ordering Guide