Datasheet ADP124, ADP125 (Analog Devices) - 3
制造商 | Analog Devices |
描述 | 5.5 V Input, 500 mA, Low Quiescent Current, CMOS Linear Regulators |
页数 / 页 | 20 / 3 — Data Sheet. ADP124/ADP125. SPECIFICATIONS. Table 1. Parameter. Symbol. … |
修订版 | D |
文件格式/大小 | PDF / 1.2 Mb |
文件语言 | 英语 |
Data Sheet. ADP124/ADP125. SPECIFICATIONS. Table 1. Parameter. Symbol. Test Conditions. Min. Typ. Max. Unit
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Data Sheet ADP124/ADP125 SPECIFICATIONS
Unless otherwise noted, VIN = (VOUT + 0.5 V) or 2.3 V, whichever is greater; ADJ connected to VOUT; IOUT = 10 mA; CIN = 1.0 µF; COUT = 1.0 µF; TA = 25°C.
Table 1. Parameter Symbol Test Conditions Min Typ Max Unit
INPUT VOLTAGE RANGE VIN 2.3 5.5 V OPERATING SUPPLY CURRENT1 IGND IOUT = 0 µA 45 µA IOUT = 0 µA, TJ = −40°C to +125°C 105 µA IOUT = 1 mA 60 µA IOUT = 1 mA, TJ = −40°C to +125°C 120 µA IOUT = 250 mA 160 µA IOUT = 250 mA, TJ = −40°C to +125°C 210 µA IOUT = 500 mA 210 µA IOUT = 500 mA, TJ = −40°C to +125°C 280 µA SHUTDOWN CURRENT ISD EN = GND 0.1 µA EN = GND, TJ = −40°C to +125°C 1 µA OUTPUT VOLTAGE ACCURACY2 VOUT Fixed Output IOUT = 10 mA −1 +1 % 100 µA < IOUT < 500 mA, VIN = (VOUT + 0.5 V) to 5.5 V, −2 +1.5 % TJ = −40°C to +125°C Adjustable Output IOUT = 10 mA 0.495 0.500 0.505 V 100 µA < IOUT < 500 mA, VIN = 2.3 V to 5.5 V, 0.485 0.500 0.515 V TJ = −40°C to +125°C LINE REGULATION ∆VOUT/∆VIN VIN = VIN = 2.3 V to 5.5 V, TJ = −40°C to +125°C −0.05 +0.05 %/V LOAD REGULATION3 ∆VOUT/∆IOUT IOUT = 1 mA to 500 mA 0.0005 %/mA IOUT = 1 mA to 500 mA, TJ = −40°C to +125°C 0.001 %/mA ADJ INPUT BIAS CURRENT ADJI-BIAS 2.3 V ≤ VIN ≤ 5.5 V, ADJ connected to VOUT 15 nA DROPOUT VOLTAGE4 VDROPOUT IOUT = 10 mA, VOUT > 2.3 V 3 mV IOUT = 10 mA, TJ = −40°C to +125°C 5 mV IOUT = 250 mA, VOUT > 2.3 V 65 mV IOUT = 250 mA, TJ = −40°C to +125°C 120 mV IOUT = 500 mA, VOUT > 2.3V 130 mV IOUT = 500 mA, TJ = −40°C to +125°C 230 mV START-UP TIME5 tSTART-UP VOUT = 3.0 V 350 µs CURRENT LIMIT THRESHOLD6 ILIMIT 550 750 1000 mA THERMAL SHUTDOWN Thermal Shutdown Threshold TSSD TJ rising 150 °C Thermal Shutdown Hysteresis TSSD-HYS 15 °C EN INPUT EN Input Logic High VIH 2.3 V ≤ VIN ≤ 5.5 V 1.2 V EN Input Logic Low VIL 2.3 V ≤ VIN ≤ 5.5 V 0.4 V EN Input Leakage Current VI-LEAKAGE EN = VIN or GND 0.1 µA EN = VIN or GND, TJ = −40°C to +125°C 1 µA UNDERVOLTAGE LOCKOUT UVLO Input Voltage Rising UVLORISE TJ = −40°C to +125°C 2.1 V Input Voltage Falling UVLOFALL TJ = −40°C to +125°C 1.5 V Hysteresis UVLOHYS TA = 25°C 125 mV Rev. D | Page 3 of 20 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUITS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS RECOMMENDED CAPACITOR SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL DATA THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION CAPACITOR SELECTION Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties UNDERVOLTAGE LOCKOUT ENABLE FEATURE CURRENT LIMIT AND THERMAL OVERLOAD PROTECTION THERMAL CONSIDERATIONS JUNCTION TEMPERATURE CALCULATIONS PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE