Datasheet ADP5030 (Analog Devices) - 6

制造商Analog Devices
描述Dual, 200 mA, High Performance RF LDO with Load Switch
页数 / 页20 / 6 — ADP5030. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. BALL A1 INDICATOR. …
修订版B
文件格式/大小PDF / 813 Kb
文件语言英语

ADP5030. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. BALL A1 INDICATOR. VOUT3. MSEL. EN2. VOUT2. VIN2. GPIN3. GPIN2. VIN1. GPOUT3 GPOUT2

ADP5030 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS BALL A1 INDICATOR VOUT3 MSEL EN2 VOUT2 VIN2 GPIN3 GPIN2 VIN1 GPOUT3 GPOUT2

该数据表的模型线

文件文字版本

ADP5030 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS BALL A1 INDICATOR 1 2 3 4 VOUT3 MSEL EN2 VOUT2 A VIN2 GPIN3 GPIN2 VIN1 B GPOUT3 GPOUT2 GPIN1 VOUT1 C VIN3 GPOUT1 GND EN1 D TOP VIEW
2 0
(BALL SIDE DOWN)
0 3-
Not to Scale
89 07 Figure 2. Pin Configuration, Top View
Table 5. Pin Function Descriptions Pin No. Mnemonic Description
A1 VOUT3 Load Switch Output. A2 MSEL Select Activation Logic for LDO2 and Load Switch. Connect MSEL to GND to select Mode 1. Connect MSEL to VIN1 to select Mode 2. A3 EN2 Enable VOUT2 and VOUT3. When MSEL is set to Logic 0 (Mode 1), VOUT2/VOUT3 activation is the logic NOR of EN2 with GPIN1. When MSEL is set to Logic 1 (Mode 2), VOUT2/VOUT3 activation is the logic AND of EN2 with NOT GPIN1. A4 VOUT2 LDO2 Output. B1 VIN2 Digital Supply Input. B2 GPIN3 Input to Level Shifter. B3 GPIN2 Input to Level Shifter. B4 VIN1 System Supply. C1 GPOUT3 Output of Level Shifter. C2 GPOUT2 Output of Level Shifter. C3 GPIN1 Input to Level Shifter. C4 VOUT1 LDO1 Output. D1 VIN3 Logic Translator Supply. D2 GPOUT1 Output of Level Shifter. D3 GND Ground. D4 EN1 Enable VOUT1. Rev. B | Page 6 of 6 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL DATA THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION LDO2 AND LOAD SWITCH ACTIVATION LOGIC SEQUENCING CAPACITOR SELECTION Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties UNDERVOLTAGE LOCKOUT ENABLE FEATURE CURRENT-LIMIT AND THERMAL OVERLOAD PROTECTION THERMAL CONSIDERATIONS PCB LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE