Datasheet ADP130 (Analog Devices) - 6
| 制造商 | Analog Devices |
| 描述 | 350 mA, Low VIN, Low Quiescent Current, CMOS Linear Regulator |
| 页数 / 页 | 20 / 6 — ADP130. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. VIN 1. … |
| 修订版 | C |
| 文件格式/大小 | PDF / 409 Kb |
| 文件语言 | 英语 |
ADP130. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. VIN 1. VOUT. GND 2. TOP VIEW. (Not to Scale). EN 3. VBIAS
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文件文字版本
ADP130 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VIN 1 5 VOUT ADP130 GND 2 TOP VIEW (Not to Scale) EN 3 4 VBIAS
03 0 3- 96 06 Figure 3. Pin Configuration
Table 5. Pin Function Descriptions Pin No. Mnemonic Description
1 VIN Regulator Input Supply. Bypass VIN to GND with a capacitor of 1 μF or greater. 2 GND Ground. 3 EN Enable Input. Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For automatic startup, connect EN to VBIAS 4 VBIAS Bias Input Supply. Connect a capacitor of 1 μF or greater between VBIAS and GND. 5 VOUT Regulated Output Voltage. Bypass VOUT to GND with a capacitor of 1 μF or greater. Rev. C | Page 6 of 20 Document Outline Features Applications Typical Application Circuits General Description Table of Contents Revision History Specifications Input and Output Capacitor: Recommended Specifications Absolute Maximum Ratings Thermal Data Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Applications Information Capacitor Selection Output Capacitor Input Bypass Capacitor Bias Capacitor Input, Bias, and Output Capacitor Properties Undervoltage Lockout Enable Feature Current Limit and Thermal Overload Protection Thermal Considerations Junction Temperature Calculations PCB Layout Considerations Outline Dimensions Ordering Guide
03 0 3- 96 06 Figure 3. Pin Configuration
Table 5. Pin Function Descriptions Pin No. Mnemonic Description
1 VIN Regulator Input Supply. Bypass VIN to GND with a capacitor of 1 μF or greater. 2 GND Ground. 3 EN Enable Input. Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For automatic startup, connect EN to VBIAS 4 VBIAS Bias Input Supply. Connect a capacitor of 1 μF or greater between VBIAS and GND. 5 VOUT Regulated Output Voltage. Bypass VOUT to GND with a capacitor of 1 μF or greater. Rev. C | Page 6 of 20 Document Outline Features Applications Typical Application Circuits General Description Table of Contents Revision History Specifications Input and Output Capacitor: Recommended Specifications Absolute Maximum Ratings Thermal Data Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Applications Information Capacitor Selection Output Capacitor Input Bypass Capacitor Bias Capacitor Input, Bias, and Output Capacitor Properties Undervoltage Lockout Enable Feature Current Limit and Thermal Overload Protection Thermal Considerations Junction Temperature Calculations PCB Layout Considerations Outline Dimensions Ordering Guide