Datasheet EFM8LB1 (Silicon Labs) - 10

EFM8LB1 Data Sheet System Overview
3.4 Clocking
The CPU core and peripheral subsystem may be clocked by both internal and external oscillator resources. By default, the system clock comes up running from the 24.5 MHz oscillator divided by 8. The clock control system offers the following features: • Provides clock to core and peripherals. • 24.5 MHz internal oscillator (HFOSC0), accurate to ±2% over supply and temperature corners. • 72 MHz internal oscillator (HFOSC1), accurate to ±2% over supply and temperature corners. • 80 kHz low-frequency oscillator (LFOSC0). • External RC and CMOS clock options (EXTCLK and EXTOSC). • Clock divider with eight settings for flexible clock scaling: • Divide the selected clock source by 1, 2, 4, 8, 16, 32, 64, or 128. • HFOSC0 and HFOSC1 include 1.5x pre-scalers for further flexibility.
3.5 Counters/Timers and PWM Programmable Counter Array (PCA0)
The programmable counter array (PCA) provides multiple channels of enhanced timer and PWM functionality while requiring less CPU intervention than standard counter/timers. The PCA consists of a dedicated 16-bit counter/timer and one 16-bit capture/compare mod- ule for each channel. The counter/timer is driven by a programmable timebase that has flexible external and internal clocking options. Each capture/compare module may be configured to operate independently in one of five modes: Edge-Triggered Capture, Software Timer, High-Speed Output, Frequency Output, or Pulse-Width Modulated (PWM) Output. Each capture/compare module has its own associated I/O line (CEXn) which is routed through the crossbar to port I/O when enabled. • 16-bit time base • Programmable clock divisor and clock source selection • Up to six independently-configurable channels • 8, 9, 10, 11 and 16-bit PWM modes (center or edge-aligned operation) • Output polarity control • Frequency output mode • Capture on rising, falling or any edge • Compare function for arbitrary waveform generation • Software timer (internal compare) mode • Can accept hardware “kill” signal from comparator 0 or comparator 1
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| Building a more connected world. Rev. 1.3 | 10 Document Outline 1. Feature List 2. Ordering Information 3. System Overview 3.1 Introduction 3.2 Power 3.3 I/O 3.4 Clocking 3.5 Counters/Timers and PWM 3.6 Communications and Other Digital Peripherals 3.7 Analog 3.8 Reset Sources 3.9 Debugging 3.10 Bootloader 4. Electrical Specifications 4.1 Electrical Characteristics 4.1.1 Recommended Operating Conditions 4.1.2 Power Consumption 4.1.3 Reset and Supply Monitor 4.1.4 Flash Memory 4.1.5 Power Management Timing 4.1.6 Internal Oscillators 4.1.7 External Clock Input 4.1.8 External Oscillator 4.1.9 ADC 4.1.10 Voltage Reference 4.1.11 Temperature Sensor 4.1.12 1.8 V Internal LDO Voltage Regulator 4.1.13 DACs 4.1.14 Comparators 4.1.15 Configurable Logic 4.1.16 Port I/O 4.1.17 SMBus 4.2 Thermal Conditions 4.3 Absolute Maximum Ratings 5. Typical Connection Diagrams 5.1 Power 5.2 Debug 5.3 Other Connections 6. Pin Definitions 6.1 EFM8LB1x-QFN32 Pin Definitions 6.2 EFM8LB1x-QFP32 Pin Definitions 6.3 EFM8LB1x-QFN24 Pin Definitions 6.4 EFM8LB1x-QSOP24 Pin Definitions 7. QFN32 Package Specifications 7.1 Package Dimensions 7.2 PCB Land Pattern 7.3 Package Marking 8. QFP32 Package Specifications 8.1 Package Dimensions 8.2 PCB Land Pattern 8.3 Package Marking 9. QFN24 Package Specifications 9.1 Package Dimensions 9.2 PCB Land Pattern 9.3 Package Marking 10. QSOP24 Package Specifications 10.1 Package Dimensions 10.2 PCB Land Pattern 10.3 Package Marking 11. Revision History