Datasheet AD539 (Analog Devices) - 10

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AD539 THEORY OF OPERATION CIRCUIT DESCRIPTION GENERAL RECOMMENDATIONS
Figure 18 shows a simplified schematic of the AD539. Q1 to Q6 The AD539 is a high speed circuit and requires considerable are large-geometry transistors designed for low distortion and care to achieve its full performance potential. A high quality low noise. Emitter-area scaling further reduces distortion: Q1 is ground plane should be used with the device either soldered three times larger than Q2; Q4 and Q5 are each three times directly into the board or mounted in a low profile socket. In larger than Q3 and Q6 and are twice as large as Q1 and Q2. A Figure 18, an open triangle denotes a direct, short connection stable reference current of IREF = 1.375 mA is produced by a to this ground plane; the BASE COMMON pins (Pin 12 and band gap reference circuit and applied to the common emitter Pin 13) are especially prone to unwanted signal pickup. Power node of a controlled cascode formed by Q1 and Q2. When VX = supply decoupling capacitors of 0.1 μF to 1 μF should be 0 V, all of IREF flows in Q1 due to the action of the high gain connected from the +VS and −VS pins (Pin 4 and Pin 5) to the control amplifier, which lowers the voltage on the base of Q2. ground plane. In applications using external high speed op As VX is raised, the fraction of IREF flowing in Q2 is forced to amps, use separate supply decoupling. It is good practice to balance the control current, VX/2.5 kΩ. At the full-scale value of insert small (10 Ω) resistors between the primary supply and VX (3 V) this fraction is 0.873. Because the base of Q1, Q4, and the decoupling capacitor. Q5 are at ground potential and the bases of Q2, Q3, and Q6 are The control amplifier compensation capacitor, CC, should commoned, all three controlled cascodes divide the current likewise have short leads to ground and a minimum value of applied to their emitter nodes in the same proportion. The 3 nF. Unless maximum control bandwidth is essential, it is control loop is stabilized by the external capacitor, CC. advisable to use a larger value of 0.01 μF to 0.1 μF to improve The signal voltages, VY1 and VY2 (generically referred to as VY), the signal channel phase response, high frequency crosstalk, are first converted to currents by voltage-to-current converters and high frequency distortion. The control bandwidth is with a gm of 575 μmhos. Thus, the full-scale input of ±2 V inversely proportional to this capacitance, typically 2 MHz for CC = becomes a current of ±1.15 mA, which is superimposed on a 0.01 μF, VX = 1.7 V. The bandwidth and pulse response of the bias of 2.75 mA and applied to the common emitter node of control channel can be improved by using a feedforward controlled cascode Q3/Q4 or Q5/Q6. As previously explained, capacitor of 5% to 20% the value of CC between the VX and the proportion of this current steered to the output node is HF COMP pins (Pin 1 and Pin 2). Optimum transient response linearly dependent on VX. Therefore, for full-scale VX and VY results when the rise/fall time of VX are commensurate with the inputs, a signal of ±1 mA (0.873 × ±1.15 mA) and a bias control channel response time. component of 2.4 mA (0.873 × 2.75 mA) appear at the output. VX should not exceed the specified range of 0 V to 3 V. The ac The bias component absorbed by the 1.25 kΩ resistors also gain is zero for VX < 0 V but there remains a feedforward path connected to VX and the resulting signal current can be applied (see Figure 18) causing control feedthrough. Recovery time to an external load resistor (in which case scaling is not from negative values of VX can be improved by adding a small accurate) or can be forced into either or both of the 6 kΩ signal Schottky diode with its cathode connected to HF COMP feedback resistors (to the Z and W nodes) by an external op (Pin 2) and its anode grounded. This constrains the voltage amp. In the latter case, scaling accuracy is guaranteed. swing on CC. Above VX = 3.2 V, the ac gain limits at its maximum value, but any overdrive appears as control feedthrough at the output.
VX 1 0V TO +3V FS 2.5kΩ CONTROL 1.25kΩ 1.25kΩ AMPLIFIER 1.2mA FS CHAN1 6kΩ 6kΩ CHAN2 14 16 W1 W2 9 11 OUTPUT OUTPUT 6kΩ 6kΩ 15 Z1 Z2 10 ±1mA FS ±1mA FS OUTPUT 8 COMMON HF COMP BASE COMMON 13 Q1 Q2 2 Q3 Q4 12 Q5 Q6 CC (EXT) I 3nF MIN REF = 1.375mA VY1 VY2 +VS 4 BAND-GAP 3 6 ±2V FS ±2V FS REFERENCE –VS 5 GENERATOR
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INPUT COMMON
67 09 Figure 18. Simplified Schematic of AD539 Multiplier (16-Lead SBDIP and PDIP Shown) Rev. B | Page 10 of 20 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION CIRCUIT DESCRIPTION GENERAL RECOMMENDATIONS TRANSFER FUNCTION DUAL SIGNAL CHANNELS COMMON CONTROL CHANNEL FLEXIBLE SCALING APPLICATIONS INFORMATION BASIC MULTIPLIER CONNECTIONS Signal Channel AC and Transient Response Minimal Wideband Configurations Differential Configurations A 50 MHZ VOLTAGE-CONTROLLED AMPLIFIER BASIC DIVIDER CONNECTIONS Standard Scaling OUTLINE DIMENSIONS ORDERING GUIDE