Datasheet PE43614 (pSemi) - 2
| 制造商 | pSemi |
| 描述 | UltraCMOS RF Digital Step Attenuator, 9 kHz–45 GHz |
| 页数 / 页 | 23 / 2 — PE43614. UltraCMOS® RF Digital Step Attenuator. Optional External VSS … |
| 文件格式/大小 | PDF / 1.2 Mb |
| 文件语言 | 英语 |
PE43614. UltraCMOS® RF Digital Step Attenuator. Optional External VSS Control. Table 2. Absolute Maximum Ratings. Table 1
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PE43614 UltraCMOS® RF Digital Step Attenuator
pSemi’s HaRP technology enhancements deliver high linearity and excel ent harmonics performance. It is an innovative feature of the UltraCMOS process, offering the performance of GaAs with the economy and integration of conventional CMOS.
Optional External VSS Control
For proper operation, the VSS_EXT control pin must be grounded or tied to the VSS voltage specified in
Table 2
. When the VSS_EXT control pin is grounded, FETs in the switch are biased with an internal negative voltage generator. For applications that require the lowest possible spur performance, VSS_EXT can be applied external y to bypass the internal negative voltage generator.
Absolute Maximum Ratings
Exceeding absolute maximum ratings listed in
Table 1
may cause permanent damage. Operation should be restricted to the limits in
Table 2
. Operation between operating range maximum and absolute maximum for extended periods may reduce reliability.
ESD Precautions
When handling this UltraCMOS device, observe the same precautions as with any other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified in
Table 1
.
Latch-up Immunity
Unlike conventional CMOS devices, UltraCMOS devices are immune to latch-up.
Table 1 • Absolute Maximum Ratings for the PE43614 Parameter/Condition Min Max Unit
Positive supply voltage, VDD –0.3 5.5 V Negative supply voltage, VSS_EXT –3.6 0.3 V Digital input voltage –0.3 3.6 V Maximum junction temperature +150 °C Storage temperature range –65 +150 °C ESD voltage HBM, al pins
(1)
1000 V ESD voltage CDM, al pins
(2)
500 V
Notes:
1) Human body model (MIL–STD 883 Method 3015) 2) Charged device model (JEDEC JESD22-C101). Page 2 of 23 DOC-93670-2 – (06/2020) www.psemi.com Document Outline Features Applications Product Description Optional External VSS Control Absolute Maximum Ratings ESD Precautions Latch-up Immunity Recommended Operating Conditions Electrical Specifications Switching Frequency Spur-free Performance Glitch-safe Attenuation State The PE43614 features a novel architecture to provide safe transition behavior when changing attenuation states. When RF input power is applied, positive output power spikes are prevented during attenuation state changes by optimized internal timing c... Truth Tables Serial Addressable Register Map Programming Options Parallel/Serial Selection Parallel Mode Interface For direct parallel programming, the LE line should be pulled HIGH. Changing attenuation state control values changes the device state to new attenuation. Direct mode is ideal for manual control of the device (using hardwire, switches, or jumpers). Serial-Addressable Interface Power-up Control Settings Typical Performance Data Pin Configuration Packaging Information Moisture Sensitivity Level Package Drawing Top-Marking Specification Tape and Reel Specification Ordering Information
PE43614 UltraCMOS® RF Digital Step Attenuator
pSemi’s HaRP technology enhancements deliver high linearity and excel ent harmonics performance. It is an innovative feature of the UltraCMOS process, offering the performance of GaAs with the economy and integration of conventional CMOS.
Optional External VSS Control
For proper operation, the VSS_EXT control pin must be grounded or tied to the VSS voltage specified in
Table 2
. When the VSS_EXT control pin is grounded, FETs in the switch are biased with an internal negative voltage generator. For applications that require the lowest possible spur performance, VSS_EXT can be applied external y to bypass the internal negative voltage generator.
Absolute Maximum Ratings
Exceeding absolute maximum ratings listed in
Table 1
may cause permanent damage. Operation should be restricted to the limits in
Table 2
. Operation between operating range maximum and absolute maximum for extended periods may reduce reliability.
ESD Precautions
When handling this UltraCMOS device, observe the same precautions as with any other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified in
Table 1
.
Latch-up Immunity
Unlike conventional CMOS devices, UltraCMOS devices are immune to latch-up.
Table 1 • Absolute Maximum Ratings for the PE43614 Parameter/Condition Min Max Unit
Positive supply voltage, VDD –0.3 5.5 V Negative supply voltage, VSS_EXT –3.6 0.3 V Digital input voltage –0.3 3.6 V Maximum junction temperature +150 °C Storage temperature range –65 +150 °C ESD voltage HBM, al pins
(1)
1000 V ESD voltage CDM, al pins
(2)
500 V
Notes:
1) Human body model (MIL–STD 883 Method 3015) 2) Charged device model (JEDEC JESD22-C101). Page 2 of 23 DOC-93670-2 – (06/2020) www.psemi.com Document Outline Features Applications Product Description Optional External VSS Control Absolute Maximum Ratings ESD Precautions Latch-up Immunity Recommended Operating Conditions Electrical Specifications Switching Frequency Spur-free Performance Glitch-safe Attenuation State The PE43614 features a novel architecture to provide safe transition behavior when changing attenuation states. When RF input power is applied, positive output power spikes are prevented during attenuation state changes by optimized internal timing c... Truth Tables Serial Addressable Register Map Programming Options Parallel/Serial Selection Parallel Mode Interface For direct parallel programming, the LE line should be pulled HIGH. Changing attenuation state control values changes the device state to new attenuation. Direct mode is ideal for manual control of the device (using hardwire, switches, or jumpers). Serial-Addressable Interface Power-up Control Settings Typical Performance Data Pin Configuration Packaging Information Moisture Sensitivity Level Package Drawing Top-Marking Specification Tape and Reel Specification Ordering Information