Datasheet AD8421 (Analog Devices) - 10
| 制造商 | Analog Devices |
| 描述 | 3 nV /√Hz, Low Power Instrumentation Amplifier |
| 页数 / 页 | 28 / 10 — AD8421. Data Sheet. TYPICAL PERFORMANCE CHARACTERISTICS. 600. 500. 400. S … |
| 文件格式/大小 | PDF / 682 Kb |
| 文件语言 | 英语 |
AD8421. Data Sheet. TYPICAL PERFORMANCE CHARACTERISTICS. 600. 500. 400. S T. 300. UNI. 200. 100. –60. –40. –20. –400. –300. –200. –100
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AD8421 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = ±15 V, VREF = 0 V, RL = 2 kΩ, unless otherwise noted.
600 600 500 500 400 400 S T S 300 IT UNI 300 UN 200 200 100 100 0 0 –60 –40 –20 0 20 40 60
03 0
–400 –300 –200 –100 0 100 200 300 400
006 3-
INPUT OFFSET VOLTAGE (µV)
23-
OUTPUT OFFSET VOLTAGE (µV)
101 012 1 Figure 4. Typical Distribution of Input Offset Voltage Figure 7. Typical Distribution of Output Offset Voltage
1800 1200 1500 1000 1200 800 S IT S 900 IT 600 UN UN 600 400 300 200 0–2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 0
004
–2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0
007
INPUT BIAS CURRENT (nA)
10123-
INPUT OFFSET CURRENT (nA)
123- 10 Figure 5. Typical Distribution of Input Bias Current Figure 8. Typical Distribution of Input Offset Current
1600 1400 1400 1200 1200 1000 1000 S 800 IT S IT 800 UN UN 600 600 400 400 200 200 0–20 –15 –10 –5 0 5 10 15 20
005
0 –120 –90 –60 –30 0 30 60 90 120
08 -0
PSRR (µV/V)
10123-
CMRR (µV/V)
123 10 Figure 6. Typical Distribution of PSRR (G = 1) Figure 9. Typical Distribution of CMRR (G = 1) Rev. 0 | Page 10 of 28 Document Outline FEATURES APPLICATIONS PIN CONNECTION DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AR AND BR GRADES ARM AND BRM GRADES ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ARCHITECTURE GAIN SELECTION RG Power Dissipation REFERENCE TERMINAL INPUT VOLTAGE RANGE LAYOUT Common-Mode Rejection Ratio over Frequency Power Supplies and Grounding Reference Pin INPUT BIAS CURRENT RETURN PATH INPUT VOLTAGES BEYOND THE SUPPLY RAILS Input Voltages Beyond the Maximum Ratings RADIO FREQUENCY INTERFERENCE (RFI) CALCULATING THE NOISE OF THE INPUT STAGE Source Resistance Noise Voltage Noise of the Instrumentation Amplifier Current Noise of the Instrumentation Amplifier Total Noise Density Calculation APPLICATIONS INFORMATION DIFFERENTIAL OUTPUT CONFIGURATION DRIVING AN ADC OUTLINE DIMENSIONS ORDERING GUIDE
TA = 25°C, VS = ±15 V, VREF = 0 V, RL = 2 kΩ, unless otherwise noted.
600 600 500 500 400 400 S T S 300 IT UNI 300 UN 200 200 100 100 0 0 –60 –40 –20 0 20 40 60
03 0
–400 –300 –200 –100 0 100 200 300 400
006 3-
INPUT OFFSET VOLTAGE (µV)
23-
OUTPUT OFFSET VOLTAGE (µV)
101 012 1 Figure 4. Typical Distribution of Input Offset Voltage Figure 7. Typical Distribution of Output Offset Voltage
1800 1200 1500 1000 1200 800 S IT S 900 IT 600 UN UN 600 400 300 200 0–2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 0
004
–2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0
007
INPUT BIAS CURRENT (nA)
10123-
INPUT OFFSET CURRENT (nA)
123- 10 Figure 5. Typical Distribution of Input Bias Current Figure 8. Typical Distribution of Input Offset Current
1600 1400 1400 1200 1200 1000 1000 S 800 IT S IT 800 UN UN 600 600 400 400 200 200 0–20 –15 –10 –5 0 5 10 15 20
005
0 –120 –90 –60 –30 0 30 60 90 120
08 -0
PSRR (µV/V)
10123-
CMRR (µV/V)
123 10 Figure 6. Typical Distribution of PSRR (G = 1) Figure 9. Typical Distribution of CMRR (G = 1) Rev. 0 | Page 10 of 28 Document Outline FEATURES APPLICATIONS PIN CONNECTION DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AR AND BR GRADES ARM AND BRM GRADES ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ARCHITECTURE GAIN SELECTION RG Power Dissipation REFERENCE TERMINAL INPUT VOLTAGE RANGE LAYOUT Common-Mode Rejection Ratio over Frequency Power Supplies and Grounding Reference Pin INPUT BIAS CURRENT RETURN PATH INPUT VOLTAGES BEYOND THE SUPPLY RAILS Input Voltages Beyond the Maximum Ratings RADIO FREQUENCY INTERFERENCE (RFI) CALCULATING THE NOISE OF THE INPUT STAGE Source Resistance Noise Voltage Noise of the Instrumentation Amplifier Current Noise of the Instrumentation Amplifier Total Noise Density Calculation APPLICATIONS INFORMATION DIFFERENTIAL OUTPUT CONFIGURATION DRIVING AN ADC OUTLINE DIMENSIONS ORDERING GUIDE