Datasheet AD8251 (Analog Devices) - 3
| 制造商 | Analog Devices |
| 描述 | 10 MHz, G = 1, 2, 4, 8 iCMOS Programmable Gain Instrumentation Amplifier |
| 页数 / 页 | 24 / 3 — AD8251. SPECIFICATIONS. Table 2. Parameter. Conditions. Min. Typ. Max. … |
| 修订版 | B |
| 文件格式/大小 | PDF / 646 Kb |
| 文件语言 | 英语 |
AD8251. SPECIFICATIONS. Table 2. Parameter. Conditions. Min. Typ. Max. Unit
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AD8251 SPECIFICATIONS
+VS = 15 V, −VS = −15 V, VREF = 0 V @ TA = 25°C, G = 1, RL = 2 kΩ, unless otherwise noted.
Table 2. Parameter Conditions Min Typ Max Unit
COMMON-MODE REJECTION RATIO (CMRR) CMRR to 60 Hz with 1 kΩ Source Imbalance +IN = −IN = −10 V to +10 V G = 1 80 98 dB G = 2 86 104 dB G = 4 92 110 dB G = 8 98 110 dB CMRR to 50 kHz +IN = −IN = −10 V to +10 V G = 1 80 dB G = 2 84 dB G = 4 86 dB G = 8 86 dB NOISE Voltage Noise, 1 kHz, RTI G = 1 40 nV/√Hz G = 2 27 nV/√Hz G = 4 22 nV/√Hz G = 8 18 nV/√Hz 0.1 Hz to 10 Hz, RTI G = 1 2.5 μV p-p G = 2 2.5 μV p-p G = 4 1.8 μV p-p G = 8 1.2 μV p-p Current Noise, 1 kHz 5 pA/√Hz Current Noise, 0.1 Hz to 10 Hz 60 pA p-p VOLTAGE OFFSET Offset RTI VOS G = 1, 2, 4, 8 ±(70 + 200/G) ±(200 + 600/G) μV Over Temperature T = −40°C to +85°C ±(90 + 300/G) ±(260 + 900/G) μV Average TC T = −40°C to +85°C ±(0.6 + 1.5/G) ±(1.2 + 5/G) μV/°C Offset Referred to the Input vs. Supply (PSR) VS = ±5 V to ±15 V ±(2 + 7/G) ±(6 + 20/G) μV/V INPUT CURRENT Input Bias Current 5 30 nA Over Temperature T = −40°C to +85°C 40 nA Average TC T = −40°C to +85°C 400 pA/°C Input Offset Current 5 30 nA Over Temperature T = −40°C to +85°C 30 nA Average TC T = −40°C to +85°C 160 pA/°C DYNAMIC RESPONSE Small Signal −3 dB Bandwidth G = 1 10 MHz G = 2 10 MHz G = 4 8 MHz G = 8 2.5 MHz Settling Time 0.01% ΔOUT = 10 V step G = 1 615 ns G = 2 460 ns G = 4 460 ns G = 8 625 ns Rev. B | Page 3 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION GAIN SELECTION Transparent Gain Mode Latched Gain Mode Timing for Latched Gain Mode POWER SUPPLY REGULATION AND BYPASSING INPUT BIAS CURRENT RETURN PATH INPUT PROTECTION REFERENCE TERMINAL COMMON-MODE INPUT VOLTAGE RANGE LAYOUT Grounding Coupling Noise Common-Mode Rejection RF INTERFERENCE DRIVING AN ADC APPLICATIONS DIFFERENTIAL OUTPUT SETTING GAINS WITH A MICROCONTROLLER DATA ACQUISITION OUTLINE DIMENSIONS ORDERING GUIDE
+VS = 15 V, −VS = −15 V, VREF = 0 V @ TA = 25°C, G = 1, RL = 2 kΩ, unless otherwise noted.
Table 2. Parameter Conditions Min Typ Max Unit
COMMON-MODE REJECTION RATIO (CMRR) CMRR to 60 Hz with 1 kΩ Source Imbalance +IN = −IN = −10 V to +10 V G = 1 80 98 dB G = 2 86 104 dB G = 4 92 110 dB G = 8 98 110 dB CMRR to 50 kHz +IN = −IN = −10 V to +10 V G = 1 80 dB G = 2 84 dB G = 4 86 dB G = 8 86 dB NOISE Voltage Noise, 1 kHz, RTI G = 1 40 nV/√Hz G = 2 27 nV/√Hz G = 4 22 nV/√Hz G = 8 18 nV/√Hz 0.1 Hz to 10 Hz, RTI G = 1 2.5 μV p-p G = 2 2.5 μV p-p G = 4 1.8 μV p-p G = 8 1.2 μV p-p Current Noise, 1 kHz 5 pA/√Hz Current Noise, 0.1 Hz to 10 Hz 60 pA p-p VOLTAGE OFFSET Offset RTI VOS G = 1, 2, 4, 8 ±(70 + 200/G) ±(200 + 600/G) μV Over Temperature T = −40°C to +85°C ±(90 + 300/G) ±(260 + 900/G) μV Average TC T = −40°C to +85°C ±(0.6 + 1.5/G) ±(1.2 + 5/G) μV/°C Offset Referred to the Input vs. Supply (PSR) VS = ±5 V to ±15 V ±(2 + 7/G) ±(6 + 20/G) μV/V INPUT CURRENT Input Bias Current 5 30 nA Over Temperature T = −40°C to +85°C 40 nA Average TC T = −40°C to +85°C 400 pA/°C Input Offset Current 5 30 nA Over Temperature T = −40°C to +85°C 30 nA Average TC T = −40°C to +85°C 160 pA/°C DYNAMIC RESPONSE Small Signal −3 dB Bandwidth G = 1 10 MHz G = 2 10 MHz G = 4 8 MHz G = 8 2.5 MHz Settling Time 0.01% ΔOUT = 10 V step G = 1 615 ns G = 2 460 ns G = 4 460 ns G = 8 625 ns Rev. B | Page 3 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION GAIN SELECTION Transparent Gain Mode Latched Gain Mode Timing for Latched Gain Mode POWER SUPPLY REGULATION AND BYPASSING INPUT BIAS CURRENT RETURN PATH INPUT PROTECTION REFERENCE TERMINAL COMMON-MODE INPUT VOLTAGE RANGE LAYOUT Grounding Coupling Noise Common-Mode Rejection RF INTERFERENCE DRIVING AN ADC APPLICATIONS DIFFERENTIAL OUTPUT SETTING GAINS WITH A MICROCONTROLLER DATA ACQUISITION OUTLINE DIMENSIONS ORDERING GUIDE