Datasheet AD8553 (Analog Devices) - 9
| 制造商 | Analog Devices |
| 描述 | 1.8 V to 5 V Auto-Zero, In-Amp with Shutdown |
| 页数 / 页 | 20 / 9 — AD8553. 180. VCC = 1.8V. FILTER = 1kHz. FILTER = 10kHz. 160. GAIN = 100. … |
| 修订版 | A |
| 文件格式/大小 | PDF / 336 Kb |
| 文件语言 | 英语 |
AD8553. 180. VCC = 1.8V. FILTER = 1kHz. FILTER = 10kHz. 160. GAIN = 100. 140. GAIN = 10. 120. GAIN = 1. R (. 100. 10k. 100k. FREQUENCY (Hz)
该数据表的模型线
文件文字版本
AD8553 180 180 VCC = 1.8V VCC = 1.8V FILTER = 1kHz FILTER = 10kHz 160 160 GAIN = 100 GAIN = 100 140 140 GAIN = 10 GAIN = 10 120 120 ) ) B GAIN = 1 B GAIN = 1 d d R ( 100 R ( 100 CM CM 80 80 60 60
1
40
2
40
02 02 4- 4- 47 47
20
05
20
05
10 100 1k 10k 100k 10 100 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz)
Figure 20. Common-Mode Rejection (CMR) vs. Frequency Figure 23. Common-Mode Rejection (CMR) vs. Frequency
VCC = 1.8V VCC = 1.8V GAIN = 100, 1000 GAIN = 100, 1000 N N IO IO T T A A L L U PU P PO PO
5 8 02 02 4- 4- 47 47 05 05
–2 0 2 4 6 8 10 12 14 16 18 20 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10
Figure 21. Input Offset Voltage (μV) Figure 24. Input Offset Voltage Drift (μV/°C)
VCC = 1.8V VCC = 1.8V GAIN = 10 GAIN = 10 N N IO IO T T A L LA U P PU PO PO
4 7 02 02 4- 4- 47 47 05 05
0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 0 0.03 0.06 0.09 0.12 0.15 0.18 0.21 0.24 0.27 0.30
Figure 22. Input Offset Voltage (μV) Figure 25. Input Offset Voltage Drift (μV/°C) Rev. A | Page 9 of 20 Document Outline FEATURES APPLICATIONS PIN CONFIGURATION GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION HIGH PSR AND CMR 1/f NOISE CORRECTION APPLICATIONS GAIN SELECTION (GAIN-SETTING RESISTORS) REFERENCE CONNECTION DISABLE FUNCTION OUTPUT FILTERING CLOCK FEEDTHROUGH LOW IMPEDANCE OUTPUT MAXIMIZING PERFORMANCE THROUGH PROPER LAYOUT POWER SUPPLY BYPASSING INPUT OVERVOLTAGE PROTECTION CAPACITIVE LOAD DRIVE CIRCUIT DIAGRAMS/CONNECTIONS OUTLINE DIMENSIONS ORDERING GUIDE
1
40
2
40
02 02 4- 4- 47 47
20
05
20
05
10 100 1k 10k 100k 10 100 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz)
Figure 20. Common-Mode Rejection (CMR) vs. Frequency Figure 23. Common-Mode Rejection (CMR) vs. Frequency
VCC = 1.8V VCC = 1.8V GAIN = 100, 1000 GAIN = 100, 1000 N N IO IO T T A A L L U PU P PO PO
5 8 02 02 4- 4- 47 47 05 05
–2 0 2 4 6 8 10 12 14 16 18 20 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10
Figure 21. Input Offset Voltage (μV) Figure 24. Input Offset Voltage Drift (μV/°C)
VCC = 1.8V VCC = 1.8V GAIN = 10 GAIN = 10 N N IO IO T T A L LA U P PU PO PO
4 7 02 02 4- 4- 47 47 05 05
0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 0 0.03 0.06 0.09 0.12 0.15 0.18 0.21 0.24 0.27 0.30
Figure 22. Input Offset Voltage (μV) Figure 25. Input Offset Voltage Drift (μV/°C) Rev. A | Page 9 of 20 Document Outline FEATURES APPLICATIONS PIN CONFIGURATION GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION HIGH PSR AND CMR 1/f NOISE CORRECTION APPLICATIONS GAIN SELECTION (GAIN-SETTING RESISTORS) REFERENCE CONNECTION DISABLE FUNCTION OUTPUT FILTERING CLOCK FEEDTHROUGH LOW IMPEDANCE OUTPUT MAXIMIZING PERFORMANCE THROUGH PROPER LAYOUT POWER SUPPLY BYPASSING INPUT OVERVOLTAGE PROTECTION CAPACITIVE LOAD DRIVE CIRCUIT DIAGRAMS/CONNECTIONS OUTLINE DIMENSIONS ORDERING GUIDE