Datasheet AD624 (Analog Devices) - 8

AD624
directly proportional to gain i.e., input offset as measured at
Table I.
the output at G = 100 is 100 times greater than at G = 1.
Temperature
Output offset is independent of gain. At low gains, output offset
Gain Coefficient Pin 3
drift is dominant, while at high gains input offset drift domi-
(Nominal) (Nominal) to Pin Connect Pins
nates. Therefore, the output offset voltage drift is normally specified as drift at G = 1 (where input effects are insignificant), 1 –0 ppm/°C – – while input offset voltage drift is given by drift specification at a 100 –1.5 ppm/°C 13 – high gain (where output offset effects are negligible). All input- 125 –5 ppm/°C 13 11 to 16 related numbers are referred to the input (RTI) which is to say 137 –5.5 ppm/°C 13 11 to 12 that the effect on the output is “G” times larger. Voltage offset 186.5 –6.5 ppm/°C 13 11 to 12 to 16 vs. power supply is also specified at one or more gain settings 200 –3.5 ppm/°C 12 – and is also RTI. 250 –5.5 ppm/°C 12 11 to 13 333 –15 ppm/°C 12 11 to 16 By separating these errors, one can evaluate the total error inde- 375 –0.5 ppm/°C 12 13 to 16 pendent of the gain setting used. In a given gain configura- 500 –10 ppm/°C 11 – tion both errors can be combined to give a total error referred to 624 –5 ppm/°C 11 13 to 16 the input (R.T.I.) or output (R.T.O.) by the following formula: 688 –1.5 ppm/°C 11 11 to 12; 13 to 16 Total Error R.T.I. = input error + (output error/gain) 831 +4 ppm/°C 11 16 to 12 Total Error R.T.O. = (Gain × input error) + output error 1000 0 ppm/°C 11 16 to 12; 13 to 11 As an illustration, a typical AD624 might have a +250 µV out- Pins 3 and 16 programs the gain according to the formula put offset and a –50 µV input offset. In a unity gain configura- tion, the total output offset would be 200 µV or the sum of the R = 40k G two. At a gain of 100, the output offset would be –4.75 mV G − 1 or: +250 µV + 100 (–50 µV) = –4.75 mV. (see Figure 29). For best results RG should be a precision resis- tor with a low temperature coefficient. An external RG affects both The AD624 provides for both input and output offset adjust- gain accuracy and gain drift due to the mismatch between it and ment. This optimizes nulling in very high precision applications the internal thin-film resistors R56 and R57. Gain accuracy is and minimizes offset voltage effects in switched gain applica- determined by the tolerance of the external RG and the absolute tions. In such applications the input offset is adjusted first at the accuracy of the internal resistors (±20%). Gain drift is determined highest programmed gain, then the output offset is adjusted at by the mismatch of the temperature coefficient of RG and the tem- G = 1. perature coefficient of the internal resistors (–15 ppm/°C typ), and the temperature coefficient of the internal interconnections.
GAIN
The AD624 includes high accuracy pretrimmed internal
+VS
gain resistors. These allow for single connection program-
–INPUT RG
ming of gains of 1, 100, 200 and 500. Additionally, a variety
1 1.5k
⍀ of gains including a pretrimmed gain of 1000 can be achieved
OR 2.105k AD624 V
⍀
OUT
through series and parallel combinations of the internal resis-
1k
⍀ tors. Table I shows the available gains and the appropriate
RG2 REFERENCE
pin connections and gain temperature coefficients.
+INPUT 40.000
The gain values achieved via the combination of internal
–V G = + 1 = 20
ⴞ
20% S 2.105
resistors are extremely useful. The temperature coefficient of the Figure 29. Operating Connections for G = 20 gain is dependent primarily on the mismatch of the temperature coefficients of the various internal resistors. Tracking of these The AD624 may also be configured to provide gain in the out- resistors is extremely tight resulting in the low gain TCs shown put stage. Figure 30 shows an H pad attenuator connected to in Table I. the reference and sense lines of the AD624. The values of R1, R2 and R3 should be selected to be as low as possible to mini- If the desired value of gain is not attainable using the inter- mize the gain variation and reduction of CMRR. Varying R2 nal resistors, a single external resistor can be used to achieve will precisely set the gain without affecting CMRR. CMRR is any gain between 1 and 10,000. This resistor connected between determined by the match of R1 and R3.
+VS INPUT +V OFFSET S R1 –INPUT 10k
⍀
NULL –INPUT 6k
⍀
RG1 RG1 R2 G = 100 G = 100 5k
⍀
AD624 VOUT G = 200 G = 200 AD624 VOUT G = 500 R G = 500 L OUTPUT RG2 SIGNAL RG2 COMMON +INPUT +INPUT R3 –V 6k
⍀
S –VS (R2||20k
⍀
) + R1 + R3)
Figure 28. Operating Connections for G = 200
G = (R2||20k
⍀
) (R1 + R2 + R3) || RL 2k
⍀ Figure 30. Gain of 2500 –8– REV. C