Datasheet MAX1086, MAX1087, MAX1088, MAX1089 (Maxim) - 4

150ksps, 10-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCs in SOT23 and TDFN TIMING CHARACTERISTICS (Figures 1 and 2)
(VDD = +2.7V to +3.6V, VREF = +2.5V for MAX1087/MAX1089, or VDD = +4.75V to +5.25V, VREF = +4.096V for MAX1086/MAX1088, 0.1µF capacitor at REF, fSCLK = 8MHz (50% duty cycle); AIN- = GND for MAX1088/MAX1089. TA = TMIN to TMAX, unless otherwise noted. Typical values at TA = +25°C.)
PARAMETERS SYMBOL CONDITIONS MIN TYP MAX UNITS
SCLK Pulse Width High tCH 38 ns SCLK Pulse Width Low tCL 38 ns SCLK Fall to DOUT Transition tDOT CLOAD = 30pF 60 ns SCLK Rise to DOUT Disable tDOD CLOAD = 30pF 100 500 ns CNVST Rise to DOUT Enable tDOE CLOAD = 30pF 80 ns CNVST Fall to MSB Valid tDOV CLOAD = 30pF 3.7 μs CNVST Pulse Width tCSW 30 ns
Note 1:
Unipolar input.
Note 2:
Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have been removed.
MAX1086–MAX1089 Note 3:
Offset nulled.
Note 4:
The absolute input range for the analog inputs is from GND to VDD. CNVST • • • tCH tCSW tCL SCLK • • • tDOE tDOT tDOD HIGH-Z HIGH-Z DOUT • • • Figure 1. Detailed Serial-Interface Timing Sequence VDD 6kΩ DOUT DOUT 6kΩ CL CL GND GND a) HIGH -Z TO VOH, VOL TO VOH, AND VOH TO HIGH -Z a) HIGH -Z TO VOL, VOH TO VOL, AND VOL TO HIGH -Z Figure 2. Load Circuits for Enable/Disable Times
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