Datasheet AOZ5317UQI (Alpha & Omega) - 8
| 制造商 | Alpha & Omega |
| 描述 | High-Current, High-Performance DrMOS Power Module |
| 页数 / 页 | 17 / 8 — AOZ5317UQI. Logic Table and Timing Diagrams. Table 1. Input Control Truth … |
| 文件格式/大小 | PDF / 2.4 Mb |
| 文件语言 | 英语 |
AOZ5317UQI. Logic Table and Timing Diagrams. Table 1. Input Control Truth Table. DISB#. SMOD#. PWM(6). GH (Not a Pin). Note:
该数据表的模型线
文件文字版本
AOZ5317UQI Logic Table and Timing Diagrams Table 1. Input Control Truth Table DISB# SMOD# PWM(6) GH (Not a Pin) GL
L X X L L H L H H L H L L L H, Forward IL L, Reverse IL H X Tri-State L L H H H H L H H L L H
Note:
6. Diode emulation mode is activated when SMOD# is LOW and PWM transition from HIGH to Tri-State. Zero Cross Detection (ZCD) at IL*Rdson(LS) = 0.5mV to turn off GL. VPWMH PWM VPWML tPDLL tPDHL GL 1V 1V tPDLU 90% VSWH tPDHU 1V 1V
Figure 1. PWM Logic Input Timing Diagram
PWM VTRI tTSSHD tTSSHD tTSSHD tTSSHD GL tTSEXIT TTSEXIT tTSEXIT tTSEXIT VSWH
Figure 2. PWM Tri-State Hold Off and Exit Timing Diagram
Rev. 2.0 June 2020
www.aosmd.com
Page 8 of 17
L X X L L H L H H L H L L L H, Forward IL L, Reverse IL H X Tri-State L L H H H H L H H L L H
Note:
6. Diode emulation mode is activated when SMOD# is LOW and PWM transition from HIGH to Tri-State. Zero Cross Detection (ZCD) at IL*Rdson(LS) = 0.5mV to turn off GL. VPWMH PWM VPWML tPDLL tPDHL GL 1V 1V tPDLU 90% VSWH tPDHU 1V 1V
Figure 1. PWM Logic Input Timing Diagram
PWM VTRI tTSSHD tTSSHD tTSSHD tTSSHD GL tTSEXIT TTSEXIT tTSEXIT tTSEXIT VSWH
Figure 2. PWM Tri-State Hold Off and Exit Timing Diagram
Rev. 2.0 June 2020
www.aosmd.com
Page 8 of 17