Datasheet ADSP-21566, ADSP-21567, ADSP-21569 (Analog Devices) - 8

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ADSP-21566/21567/21569 Addressing Spaces
The memory space is used for various situations including In addition to traditionally supported long word, normal word, • Accelerator and peripheral sources and destination mem- extended precision word, and short word addressing aliases, the ory to avoid accessing data in the external memory processors support byte addressing for the data and instruction • A location for DMA descriptors accesses. The enhanced ISA/VISA provides new instructions for accessing all sizes of data from byte space, as well as converting • Storage for additional data for the SHARC+ core to avoid word addresses to byte addresses and byte addresses to word external memory latencies and reduce external memory addresses. bandwidth • Storage for data coefficient tables cached by the
Additional Features
SHARC+ core To enhance the reliability of the application, L1 data RAMs sup- See the System Memory Protection Unit (SMPU) section for port parity error detection for every byte, and illegal opcodes are options in limiting access by the core and DMA masters. also detected (core interrupts flag both errors). Master ports of the core also detect failed external accesses.
One Time Programmable Memory (OTP) SYSTEM INFRASTRUCTURE
The processors feature 7 kb of one time programmable (OTP) memory that is memory-map accessible. This memory can be The following sections describe the system infrastructure of the programmed with custom keys and supports secure boot and ADSP-2156x processors. secure operation.
System L2 Memory I/O Memory Space
A system L2 SRAM memory of up to 8 Mb (1 MB) is available to Mapped I/Os include SPI2 or OSPI0 memory address spaces the SHARC+ core and the system DMA channels (see Table 3). (see Table 5). The L2 SRAM block is subdivided into up to eight banks to sup- port concurrent access to the L2 memory ports. Memory accesses to the L2 memory space are multicycle accesses by the SHARC+ core.
SYSTEM MEMORY MAP Table 2. L1 Block 0, Block 1, Block 2, and Block 3 SHARC+® Addressing Memory Map (Private Address Space) Extended Precision/ Short Word/ Memory Long Word (64 Bits) ISA Code (48 Bits) Normal Word (32 Bits) VISA Code (16 Bits) Byte Access (8 Bits)
L1 Block 0 SRAM 0x00048000– 0x00090000– 0x00090000– 0x00120000– 0x00240000– (1.5 Mb) 0x0004DFFF 0x00097FFF 0x0009BFFF 0x00137FFF 0x0026FFFF L1 Block 1 SRAM 0x00058000– 0x000B0000– 0x000B0000– 0x00160000– 0x002C0000– (1.5 Mb) 0x0005DFFF 0x000B7FFF 0x000BBFFF 0x00177FFF 0x002EFFFF L1 Block 2 SRAM 0x00060000– 0x000C0000– 0x000C0000– 0x00180000– 0x00300000– (1 Mb) 0x00063FFF 0x000C5554 0x000C7FFF 0x0018FFFF 0x0031FFFF L1 Block 3 SRAM 0x00070000– 0x000E0000– 0x000E0000– 0x001C0000– 0x00380000– (1 Mb) 0x00073FFF 0x000E5554 0x000E7FFF 0x001CFFFF 0x0039FFFF
Table 3. L2 Memory Addressing Map Byte Address Space Normal Word Address Space VISA Address Space ISA Address Space SHARC+ Memory1 SHARC+ Data Access SHARC+ Data Address SHARC+ Instruction Fetch Instruction Fetch
L2 RAM (2 Mb) 0x200C0000– 0x08030000– 0x00BE0000– 0x005E0000– 0x200FFFFF 0x0803FFFF 0x00BFFFFF 0x005EAAAA L2 RAM (4 Mb) 0x20080000– 0x08020000– 0x00BC0000– 0x005D5556– 0x200FFFFF 0x0803FFFF 0x00BFFFFF 0x005EAAAA L2 RAM (8 Mb) 0x20000000– 0x08000000– 0x00B80000– 0x005C0000– 0x200FFFFF 0x0803FFFF 0x00BFFFFF 0x005EAAAA Rev. 0 | Page 8 of 98 | March 2020 Document Outline System Features Memory Additional Features Applications Table of Contents Revision History General Description SHARC Processor L1 Memory L1 Master and Slave Ports L1 On-Chip Memory Bandwidth Instruction and Data Cache Core Memory-Mapped Registers (CMMR) SHARC+ Core Architecture Single-Instruction, Multiple Data (SIMD) Computational Engine Independent Parallel Computation Units Core Timer Data Register File Context Switch Universal Registers Data Address Generators (DAG) With Zero Overhead Hardware Circular Buffer Support Flexible Instruction Set Architecture (ISA) Variable Instruction Set Architecture (VISA) Single-Cycle Fetch of Instructional Four Operands Core Event Controller (CEC) Instruction Conflict Cache Branch Target Buffer (BTB)/Branch Predictor (BP) Addressing Spaces Additional Features System Infrastructure System L2 Memory One Time Programmable Memory (OTP) I/O Memory Space System Memory Map System Crossbars (SCBs) Direct Memory Access (DMA) Memory Direct Memory Access (MDMA) Extended Memory DMA Cyclic Redundant Code (CRC) Protection Event Handling System Event Controller (SEC) Trigger Routing Unit (TRU) Security Features Cryptographic Hardware Accelerators System Protection Unit (SPU) System Memory Protection Unit (SMPU) Security Features Disclaimer Safety Features Multiparity Bit Protected SHARC+ Core L1 Memories Error Correcting Code (ECC) Protected L2 Memories Parity Protected Peripheral Memories Cyclic Redundant Code (CRC) Protected Memories Signal Watchdogs System Event Controller (SEC) Memory Error Controller (MEC) Processor Peripherals Dynamic Memory Controller (DMC) Digital Audio Interface (DAI) Serial Port (SPORT) Asynchronous Sample Rate Converter (ASRC) S/PDIF-Compatible Digital Audio Receiver/Transmitter Precision Clock Generators (PCG) Universal Asynchronous Receiver/Transmitter (UART) Ports Serial Peripheral Interface (SPI) Ports Octal Serial Peripheral Interface (OSPI) Port Link Port (LP) Timers General-Purpose (GP) Timers (TIMER) Watchdog Timer (WDT) General-Purpose Counters (CNT) Media Local Bus (MediaLB) 2-Wire Controller Interface (TWI) General-Purpose I/O (GPIO) Pin Interrupts System Acceleration Finite Impulse Response (FIR) Accelerator Infinite Impulse Response (IIR) Accelerator System Design Clock Management Reset Control Unit (RCU) Clock Generation Unit (CGU) System Crystal Oscillator Clock Distribution Unit (CDU) Clock Out/External Clock Booting Power Supplies Power Management Power-Up and Power-Down Sequencing Target Board JTAG Emulator Connector System Debug System Watchpoint Unit (SWU) Debug Access Port (DAP) Development Tools Integrated Development Environments (IDEs) EZ-KIT Evaluation Board EZ-KIT Evaluation Kits Software Add Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains ADSP-2156x Detailed Signal Descriptions 400-Ball CSP_BGA Signal Descriptions GPIO Multiplexing for 400-Ball CSP_BGA Package 120-Lead LQFP Signal Descriptions GPIO Multiplexing for 120-Lead LQFP ADSP-2156x Designer Quick Reference Specifications Operating Conditions Clock Related Operating Conditions Electrical Characteristics Total Internal Power Dissipation Application Dependent Current Clock Current Data Transmission Current Absolute Maximum Ratings ESD Caution Timing Specifications Power-Up Reset Timing Clock and Reset Timing Link Ports (LPs) Serial Ports (SPORTs) Asynchronous Sample Rate Converter (ASRC)—Serial Input Port Asynchronous Sample Rate Converter (ASRC)—Serial Output Port SPI Port—Master Timing SPI0, SPI1, and SPI2 SPI Port—Slave Timing SPI0, SPI1, and SPI2 SPI Port—SPIx_RDY Slave Timing SPI Port—Open Drain Mode (ODM) Timing SPI Port—SPIx_RDY Master Timing OSPI Port—Master Timing OSPI0 Precision Clock Generator (PCG) (Direct Pin Routing) General-Purpose IO Port Timing General-Purpose I/O Timer Cycle Timing DAIx Pin to DAIx Pin Direct Routing (DAI0 Block and DAI1 Block) Up/Down Counter/Rotary Encoder Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Sony/Philips Digital Interface (S/PDIF) Transmitter S/PDIF Transmitter Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode MediaLB (MLB) Program Trace Macrocell (PTM) Timing Debug Interface (JTAG Emulation Port) Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Capacitive Loading Environmental Conditions ADSP-2156x 400-Ball BGA Ball Assignments ADSP-2156x 400-Ball BGA Ball Assignments (Numerical by Ball Number) ADSP-2156x 400-Ball BGA Ball Assignments (Alphabetical by Pin Name) Configuration of the 400-Ball CSP_BGA ADSP-2156x 120-Lead LQFP Lead Assignments ADSP-2156x 120-Lead LQFP Lead Assignments (Numerical by Lead Number) ADSP-2156x 120-Lead LQFP Lead Assignments (Alphabetical by Pin Name) Configuration of the 120-Lead LQFP Lead Configuration Outline Dimensions Surface-Mount Design Planned Automotive Production Products Planned Production Products Ordering Guide