Preliminary Datasheet ADSP-21562, ADSP-21563, ADSP-21565 (Analog Devices) - 10

ADSP-21562/21563/21565 Preliminary Technical Data System Crossbars (SCBs)
• The 1D DMA uses a linked list of four-word descriptor sets containing a link pointer, an address, a length, and a The system crossbars (SCBs) are the fundamental building configuration blocks of a switch fabric style for on-chip system bus intercon- nection. The SCBs connect system bus masters to system bus • The 2D DMA uses an array of one-word descriptor sets, slaves, providing concurrent data transfer between multiple bus specifying only the base DMA address masters and multiple bus slaves. A hierarchical model—built • The 2D DMA uses a linked list of multiword descriptor from multiple SCBs—provides a power and area efficient sys- sets, specifying all configurable parameters tem interconnection.
Memory Direct Memory Access (MDMA)
The SCBs provide the following features: The processor supports various memory direct memory access • Highly efficient, pipelined bus transfer protocol for sus- (MDMA) operations, including, tained throughput • Enhanced bandwidth MDMA channels with CRC protec- • Full-duplex bus operation for flexibility and reduced tion (32-bit bus width, run on SYSCLK) latency • Enhanced bandwidth MDMA channel (32-bit bus width, • Concurrent bus transfer support to allow multiple bus runs on SYSCLK) masters to access bus slaves simultaneously • Maximum bandwidth MDMA channel (64-bit bus width, • Protection model (privileged/secure) support for selective runs on SYCLK) bus interconnect protection
Extended Memory DMA Direct Memory Access (DMA)
Extended memory DMA supports various operating modes, The processors use direct memory access (DMA) to transfer such as delay line (which allows processor reads and writes to data within memory spaces or between a memory space and a external delay line buffers and to the external memory), with peripheral. The processors can specify data transfer operations limited core interaction and scatter/gather DMA (writes to and and return to normal processing while the fully integrated DMA from noncontiguous memory blocks). controller carries out the data transfers independent of proces- sor activity.
Cyclic Redundant Code (CRC) Protection
DMA transfers can occur between memory and a peripheral or The cyclic redundant codes (CRC) protection modules allow between one memory and another memory. Each memory to system software to calculate the signature of code, data, or both memory DMA stream uses two channels: the source channel in memory, the content of memory-mapped registers, or peri- and the destination channel. odic communication message objects. Dedicated hardware All DMA channels can transport data to and from all on-chip circuitry compares the signature with precalculated values and and off-chip memories. Programs can use two types of DMA triggers appropriate fault events. transfers: descriptor-based or register-based. Register-based For example, every 100 ms the system software initiates the sig- DMA allows the processors to program DMA control registers nature calculation of the entire memory contents and compares directly to initiate a DMA transfer. On completion, the DMA these contents with expected, precalculated values. If a mis- control registers automatically update with original setup values match occurs, a fault condition is generated through the for continuous transfer. Descriptor-based DMA transfers processor core or the trigger routing unit. require a set of parameters stored within memory to initiate a The CRC is a hardware module based on a CRC32 engine that DMA sequence. Descriptor-based DMA transfers allow computes the CRC value of the 32-bit data-words presented to multiple DMA sequences to be chained together. Program a it. The source channel of the memory to memory DMA (in DMA channel to set up and start another DMA transfer auto- memory scan mode) provides data. The data can be optionally matically after the current sequence completes. forwarded to the destination channel (memory transfer mode). The DMA engine supports the following DMA operations: The main features of the CRC peripheral are as follows: • A single linear buffer that stops on completion • Memory scan mode • A linear buffer with negative, positive, or zero stride length • Memory transfer mode • A circular autorefreshing buffer that interrupts when each • Data verify mode buffer becomes full • Data fill mode • A similar circular buffer that interrupts on fractional buf- • User-programmable CRC32 polynomial fers, such as at the halfway point • Bit and byte mirroring option (endianness) • The 1D DMA uses a set of identical ping pong buffers defined by a linked ring of two-word descriptor sets, each • Fault and error interrupt mechanisms containing a link pointer and an address • 1D and 2D fill block to initialize an array with constants • 32-bit CRC signature of a block of a memory or an MMR block Rev. PrG | Page 10 of 95 | June 2020 Document Outline System Features Memory Additional Features Applications Table of Contents Revision History General Description SHARC Processor L1 Memory L1 Master and Slave Ports L1 On-Chip Memory Bandwidth Instruction and Data Cache System Event Controller (SEC) Input Core Memory-Mapped Registers (CMMR) SHARC+ Core Architecture Single-Instruction, Multiple Data (SIMD) Computational Engine Independent Parallel Computation Units Core Timer Data Register File Context Switch Universal Registers Data Address Generators (DAG) With Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Architecture (ISA) Variable Instruction Set Architecture (VISA) Single-Cycle Fetch of Instructional Four Operands Core Event Controller (CEC) Instruction Conflict Cache Branch Target Buffer (BTB)/Branch Predictor (BP) Addressing Spaces Additional Features System Infrastructure System L2 Memory One Time Programmable Memory (OTP) I/O Memory Space System Memory Map System Crossbars (SCBs) Direct Memory Access (DMA) Memory Direct Memory Access (MDMA) Extended Memory DMA Cyclic Redundant Code (CRC) Protection Event Handling System Event Controller (SEC) Trigger Routing Unit (TRU) Security Features Cryptographic Hardware Accelerators System Protection Unit (SPU) System Memory Protection Unit (SMPU) Security Features Disclaimer Safety Features Multiparity Bit Protected SHARC+ Core L1 Memories Error Correcting Codes (ECC) Protected L2 Memories Parity-Protected Peripheral Memories Cyclic Redundant Code (CRC) Protected Memories Signal Watchdogs System Event Controller (SEC) Memory Error Controller (MEC) Processor Peripherals Dynamic Memory Controller (DMC) Digital Audio Interface (DAI) Serial Port (SPORT) Asynchronous Sample Rate Converter (ASRC) S/PDIF-Compatible Digital Audio Receiver/Transmitter Precision Clock Generators (PCG) Universal Asynchronous Receiver/Transmitter (UART) Ports Serial Peripheral Interface (SPI) Ports Octal Serial Peripheral Interface (OSPI) Port Link Port (LP) Timers General-Purpose (GP) Timers (TIMER) Watchdog Timer (WDT) General-Purpose Counters (CNT) Media Local Bus (MediaLB) 2-Wire Controller Interface (TWI) General-Purpose I/O (GPIO) Pin Interrupts System Acceleration Finite Impulse Response (FIR) Accelerator Infinite Impulse Response (IIR) Accelerator System Design Clock Management Reset Control Unit (RCU) Clock Generation Unit (CGU) System Crystal Oscillator Clock Distribution Unit (CDU) Clock Out/External Clock Booting Power Supplies Power Management Power-Up and Power-Down Sequencing Target Board JTAG Emulator Connector System Debug System Watchpoint Unit (SWU) Debug Access Port (DAP) Development Tools Integrated Development Environments (IDEs) EZ-KIT Evaluation Board EZ-KIT Evaluation Kits Software Add Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains ADSP-2156x Detailed Signal Descriptions 400-Ball CSP_BGA Signal Descriptions GPIO Multiplexing for 400-Ball CSP_BGA Package 120-Lead LQFP Signal Descriptions GPIO Multiplexing for 120-Lead LQFP ADSP-2156x Designer Quick Reference Preliminary Specifications Preliminary Operating Conditions Preliminary Clock Related Operating Conditions Preliminary Electrical Characteristics Absolute Maximum Ratings ESD Caution Timing Specifications Power-Up Reset Timing Clock and Reset Timing Link Ports (LPs) Serial Ports (SPORTs) Asynchronous Sample Rate Converter (ASRC)—Serial Input Port Asynchronous Sample Rate Converter (ASRC)—Serial Output Port SPI Port—Master Timing SPI0, SPI1, and SPI2 SPI Port—Slave Timing SPI0, SPI1, and SPI2 SPI Port—SPIx_RDY Slave Timing SPI Port—Open Drain Mode (ODM) Timing SPI Port—SPIx_RDY Master Timing OSPI Port—Master Timing OSPI0 Precision Clock Generator (PCG) (Direct Pin Routing) General-Purpose IO Port Timing General-Purpose I/O Timer Cycle Timing DAIx Pin to DAIx Pin Direct Routing (DAI0 Block and DAI1 Block) Up/Down Counter/Rotary Encoder Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Sony/Philips Digital Interface (S/PDIF) Transmitter S/PDIF Transmitter Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode MediaLB (MLB) Program Trace Macrocell (PTM) Timing Debug Interface (JTAG Emulation Port) Timing ADSP-2156x 400-Ball BGA Ball Assignments ADSP-2156x 400-Ball BGA Ball Assignments (Numerical by Ball Number) ADSP-2156x 400-Ball BGA Ball Assignments (Alphabetical by Pin Name) Configuration of the 400-Ball CSP_BGA ADSP-2156x 120-Lead LQFP Lead Assignments ADSP-2156x 120-Lead LQFP Lead Assignments (Numerical by Lead Number) ADSP-2156x 120-Lead LQFP Lead Assignments (Alphabetical by Pin Name) Configuration of the 120-Lead LQFP Lead Configuration Outline Dimensions Surface-Mount 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