Datasheet ADSP-21483, ADSP-21486, ADSP-21487, ADSP-21488, ADSP-21489 (Analog Devices) - 2
| 制造商 | Analog Devices |
| 描述 | SHARC Processor |
| 页数 / 页 | 71 / 2 — ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489. TABLE OF … |
| 修订版 | H |
| 文件格式/大小 | PDF / 1.9 Mb |
| 文件语言 | 英语 |
ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489. TABLE OF CONTENTS. REVISION HISTORY. 2/2020—Rev. G to Rev. H
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ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 TABLE OF CONTENTS
Features ... 1 ESD Sensitivity ... 21 Table of Contents ... 2 Maximum Power Dissipation ... 21 Revision History .. 2 Timing Specifications ... 22 General Description ... 3 Output Drive Currents ... 55 Family Core Architecture .. 4 Test Conditions .. 55 Family Peripheral Architecture .. 7 Capacitive Loading .. 55 I/O Processor Features ... 10 Thermal Characteristics .. 56 System Design .. 11 88-Lead LFCSP_VQ Lead Assignment ... 58 Development Tools ... 12 100-Lead LQFP_EP Lead Assignment ... 60 Additional Information .. 13 176-Lead LQFP_EP Lead Assignment ... 62 Related Signal Chains .. 13 Outline Dimensions .. 66 Pin Function Descriptions ... 14 Surface-Mount Design .. 68 Specifications .. 18 Automotive Products .. 69 Operating Conditions .. 18 Ordering Guide ... 70 Electrical Characteristics ... 19 Absolute Maximum Ratings .. 21
REVISION HISTORY 2/2020—Rev. G to Rev. H
Changes to Pin List, Power, Ground and Other .. 17 Changes to Operating Conditions ... 18 Changes to Electrical Characteristics .. 19 Changes to Thermal Characteristics .. 56 Changes to 88-Lead LFCSP_VQ Lead Assignment .. 58 Changes to 100-Lead LQFP_EP Lead Assignment ... 60 Changes to 176-Lead LQFP_EP Lead Assignment ... 62 Changes to Automotive Products .. 69 Changes to Ordering Guide ... 70 Rev. H | Page 2 of 71 | February 2020 Document Outline Features Table of Contents Revision History General Description Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Timer Data Register File Context Switch Universal Registers Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators With Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Variable Instruction Set Architecture (VISA) On-Chip Memory ROM Based Security On-Chip Memory Bandwidth Family Peripheral Architecture External Memory External Port Asynchronous Memory Controller SDRAM Controller SIMD Access to External Memory VISA and ISA Access to External Memory Pulse-Width Modulation MediaLB Digital Applications Interface (DAI) Serial Ports (SPORTs) S/PDIF-Compatible Digital Audio Receiver/Transmitter Asynchronous Sample Rate Converter (SRC) Input Data Port Precision Clock Generators Digital Peripheral Interface (DPI) Serial Peripheral (Compatible) Interface (SPI) UART Port Timers 2-Wire Interface Port (TWI) I/O Processor Features DMA Controller Delay Line DMA Scatter/Gather DMA FFT Accelerator FIR Accelerator IIR Accelerator Watchdog Timer System Design Program Booting Power Supplies Static Voltage Scaling (SVS) Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings ESD Sensitivity Maximum Power Dissipation Timing Specifications Core Clock Requirements Voltage Controlled Oscillator (VCO) Power-Up Sequencing Clock Input Clock Signals Reset Running Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Watchdog Timer Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags SDRAM Interface Timing (166 MHz SDCLK) AMI Read AMI Write Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port Pulse-Width Modulation Generators (PWM) S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave Media Local Bus Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing 2-Wire Interface (TWI)—Receive and Transmit Timing JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics Thermal Diode 88-Lead LFCSP_VQ Lead Assignment 100-Lead LQFP_EP Lead Assignment 176-Lead LQFP_EP Lead Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide
ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 TABLE OF CONTENTS
Features ... 1 ESD Sensitivity ... 21 Table of Contents ... 2 Maximum Power Dissipation ... 21 Revision History .. 2 Timing Specifications ... 22 General Description ... 3 Output Drive Currents ... 55 Family Core Architecture .. 4 Test Conditions .. 55 Family Peripheral Architecture .. 7 Capacitive Loading .. 55 I/O Processor Features ... 10 Thermal Characteristics .. 56 System Design .. 11 88-Lead LFCSP_VQ Lead Assignment ... 58 Development Tools ... 12 100-Lead LQFP_EP Lead Assignment ... 60 Additional Information .. 13 176-Lead LQFP_EP Lead Assignment ... 62 Related Signal Chains .. 13 Outline Dimensions .. 66 Pin Function Descriptions ... 14 Surface-Mount Design .. 68 Specifications .. 18 Automotive Products .. 69 Operating Conditions .. 18 Ordering Guide ... 70 Electrical Characteristics ... 19 Absolute Maximum Ratings .. 21
REVISION HISTORY 2/2020—Rev. G to Rev. H
Changes to Pin List, Power, Ground and Other .. 17 Changes to Operating Conditions ... 18 Changes to Electrical Characteristics .. 19 Changes to Thermal Characteristics .. 56 Changes to 88-Lead LFCSP_VQ Lead Assignment .. 58 Changes to 100-Lead LQFP_EP Lead Assignment ... 60 Changes to 176-Lead LQFP_EP Lead Assignment ... 62 Changes to Automotive Products .. 69 Changes to Ordering Guide ... 70 Rev. H | Page 2 of 71 | February 2020 Document Outline Features Table of Contents Revision History General Description Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Timer Data Register File Context Switch Universal Registers Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators With Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Variable Instruction Set Architecture (VISA) On-Chip Memory ROM Based Security On-Chip Memory Bandwidth Family Peripheral Architecture External Memory External Port Asynchronous Memory Controller SDRAM Controller SIMD Access to External Memory VISA and ISA Access to External Memory Pulse-Width Modulation MediaLB Digital Applications Interface (DAI) Serial Ports (SPORTs) S/PDIF-Compatible Digital Audio Receiver/Transmitter Asynchronous Sample Rate Converter (SRC) Input Data Port Precision Clock Generators Digital Peripheral Interface (DPI) Serial Peripheral (Compatible) Interface (SPI) UART Port Timers 2-Wire Interface Port (TWI) I/O Processor Features DMA Controller Delay Line DMA Scatter/Gather DMA FFT Accelerator FIR Accelerator IIR Accelerator Watchdog Timer System Design Program Booting Power Supplies Static Voltage Scaling (SVS) Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings ESD Sensitivity Maximum Power Dissipation Timing Specifications Core Clock Requirements Voltage Controlled Oscillator (VCO) Power-Up Sequencing Clock Input Clock Signals Reset Running Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Watchdog Timer Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags SDRAM Interface Timing (166 MHz SDCLK) AMI Read AMI Write Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port Pulse-Width Modulation Generators (PWM) S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave Media Local Bus Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing 2-Wire Interface (TWI)—Receive and Transmit Timing JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics Thermal Diode 88-Lead LFCSP_VQ Lead Assignment 100-Lead LQFP_EP Lead Assignment 176-Lead LQFP_EP Lead Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide