Datasheet ADSP-21483, ADSP-21486, ADSP-21487, ADSP-21488, ADSP-21489 (Analog Devices) - 5

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
S
JTAG FLAG TIMER INTERRUPT CACHE SIMD Core PM ADDRESS 24 DMD/PMD 64 5 STAGE PROGRAM SEQUENCER PM DATA 48 DAG1 DAG2 16x32 16x32 PM ADDRESS 32 SYSTEM I/F DM ADDRESS 32 USTAT 4x32-BIT PM DATA 64 PX DM DATA 64 64-BIT RF DATA RF SWAP MULTIPLIER SHIFTER ALU Rx/Fx Sx/SFx ALU SHIFTER MULTIPLIER PEx PEy 16x40-BIT 16x40-BIT MRF MRB MSB MSF 80-BIT 80-BIT ASTATx ASTATy 80-BIT 80-BIT STYKx STYKy
Figure 2. SHARC Core Block Diagram
Universal Registers
fetches conflict with PM bus data accesses are cached. This cache allows full speed execution of core, looped operations These registers can be used for general-purpose tasks. The such as digital filter multiply-accumulates, and FFT butterfly USTAT (4) registers allow easy bit manipulations (Set, Clear, processing. Toggle, Test, XOR) for all peripheral registers (control/status). The data bus exchange register (PX) permits data to be passed
Data Address Generators With Zero-Overhead Hardware
between the 64-bit PM data bus and the 64-bit DM data bus, or
Circular Buffer Support
between the 40-bit register file and the PM/DM data bus. These The two data address generators (DAGs) are used for indirect registers contain hardware to handle the data width difference. addressing and implementing circular data buffers in hardware.
Single-Cycle Fetch of Instruction and Four Operands
Circular buffers allow efficient programming of delay lines and other data structures required in digital signal processing, and The ADSP-2148x features an enhanced Harvard architecture in are commonly used in digital filters and Fourier transforms. which the data memory (DM) bus transfers data and the pro- The two DAGs contain sufficient registers to allow the creation gram memory (PM) bus transfers both instructions and data. of up to 32 circular buffers (16 primary register sets, 16 second- With the its separate program and data memory buses and on- ary). The DAGs automatically handle address pointer chip instruction cache, the processor can simultaneously fetch wraparound, reduce overhead, increase performance, and sim- four operands (two over each data bus) and one instruction plify implementation. Circular buffers can start and end at any (from the cache), all in a single cycle. memory location.
Instruction Cache Flexible Instruction Set
The processor includes an on-chip instruction cache that The 48-bit instruction word accommodates a variety of parallel enables three-bus operation for fetching an instruction and four operations, for concise programming. For example, the data values. The cache is selective—only the instructions whose processor can conditionally execute a multiply, an add, and a Rev. H | Page 5 of 71 | February 2020 Document Outline Features Table of Contents Revision History General Description Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Timer Data Register File Context Switch Universal Registers Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators With Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Variable Instruction Set Architecture (VISA) On-Chip Memory ROM Based Security On-Chip Memory Bandwidth Family Peripheral Architecture External Memory External Port Asynchronous Memory Controller SDRAM Controller SIMD Access to External Memory VISA and ISA Access to External Memory Pulse-Width Modulation MediaLB Digital Applications Interface (DAI) Serial Ports (SPORTs) S/PDIF-Compatible Digital Audio Receiver/Transmitter Asynchronous Sample Rate Converter (SRC) Input Data Port Precision Clock Generators Digital Peripheral Interface (DPI) Serial Peripheral (Compatible) Interface (SPI) UART Port Timers 2-Wire Interface Port (TWI) I/O Processor Features DMA Controller Delay Line DMA Scatter/Gather DMA FFT Accelerator FIR Accelerator IIR Accelerator Watchdog Timer System Design Program Booting Power Supplies Static Voltage Scaling (SVS) Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings ESD Sensitivity Maximum Power Dissipation Timing Specifications Core Clock Requirements Voltage Controlled Oscillator (VCO) Power-Up Sequencing Clock Input Clock Signals Reset Running Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Watchdog Timer Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags SDRAM Interface Timing (166 MHz SDCLK) AMI Read AMI Write Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port Pulse-Width Modulation Generators (PWM) S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave Media Local Bus Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing 2-Wire Interface (TWI)—Receive and Transmit Timing JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics Thermal Diode 88-Lead LFCSP_VQ Lead Assignment 100-Lead LQFP_EP Lead Assignment 176-Lead LQFP_EP Lead Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide