Datasheet ADSP-21483, ADSP-21486, ADSP-21487, ADSP-21488, ADSP-21489 (Analog Devices) - 7

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 Table 4. Internal Memory Space (5 MBits—ADSP-21486/ADSP-21487/ADSP-21489)1 IOP Registers 0x0000 0000–0x0003 FFFF Extended Precision Normal or Long Word (64 Bits) Instruction Word (48 Bits) Normal Word (32 Bits) Short Word (16 Bits)
Block 0 ROM (Reserved) Block 0 ROM (Reserved) Block 0 ROM (Reserved) Block 0 ROM (Reserved) 0x0004 0000–0x0004 7FFF 0x0008 0000–0x0008 AAA9 0x0008 0000–0x0008 FFFF 0x0010 0000–0x0011 FFFF Reserved Reserved Reserved Reserved 0x0004 8000–0x0004 8FFF 0x0008 AAAA–0x0008 BFFF 0x0009 0000–0x0009 1FFF 0x0012 0000–0x0012 3FFF Block 0 SRAM Block 0 SRAM Block 0 SRAM Block 0 SRAM 0x0004 9000–0x0004 EFFF 0x0008 C000–0x0009 3FFF 0x0009 2000–0x0009 DFFF 0x0012 4000–0x0013 BFFF Reserved Reserved Reserved Reserved 0x0004 F000–0x0004 FFFF 0x0009 4000–0x0009 FFFF 0x0009 E000–0x0009 FFFF 0x0013 C000–0x0013 FFFF Block 1 ROM (Reserved) Block 1 ROM (Reserved) Block 1 ROM (Reserved) Block 1 ROM (Reserved) 0x0005 0000–0x0005 7FFF 0x000A 0000–0x000A AAA9 0x000A 0000–0x000A FFFF 0x0014 0000–0x0015 FFFF Reserved Reserved Reserved Reserved 0x0005 8000–0x0005 8FFF 0x000A AAAA–0x000A BFFF 0x000B 0000–0x000B 1FFF 0x0016 0000–0x0016 3FFF Block 1 SRAM Block 1 SRAM Block 1 SRAM Block 1 SRAM 0x0005 9000–0x0005 EFFF 0x000A C000–0x000B 3FFF 0x000B 2000–0x000B DFFF 0x0016 4000–0x0017 BFFF Reserved Reserved Reserved Reserved 0x0005 F000–0x0005 FFFF 0x000B 4000–0x000B FFFF 0x000B E000–0x000B FFFF 0x0017 C000–0x0017 FFFF Block 2 SRAM Block 2 SRAM Block 2 SRAM Block 2 SRAM 0x0006 0000–0x0006 3FFF 0x000C 0000–0x000C 5554 0x000C 0000–0x000C 7FFF 0x0018 0000–0x0018 FFFF Reserved Reserved Reserved Reserved 0x0006 4000– 0x0006 FFFF 0x000C 5555–0x000D FFFF 0x000C 8000–0x000D FFFF 0x0019 0000–0x001B FFFF Block 3 SRAM Block 3 SRAM Block 3 SRAM Block 3 SRAM 0x0007 0000–0x0007 3FFF 0x000E 0000–0x000E 5554 0x000E 0000–0x000E 7FFF 0x001C 0000–0x001C FFFF Reserved Reserved Reserved Reserved 0x0007 4000–0x0007 FFFF 0x000E 5555–0x0000F FFFF 0x000E 8000–0x000F FFFF 0x001D 0000–0x001F FFFF 1 Some ADSP-2148x processors include a customer-definable ROM block and are not reserved as shown on this table. Contact your Analog Devices sales representative for additional details. instruction that retrieves 48-bit memory. The 32-bit section
FAMILY PERIPHERAL ARCHITECTURE
describes what this address range looks like to an instruction The ADSP-2148x family contains a rich set of peripherals that that retrieves 32-bit memory. support a wide variety of applications including high quality
ROM Based Security
audio, medical imaging, communications, military, test equip- ment, 3D graphics, speech recognition, motor control, imaging, The ADSP-2148x has a ROM security feature that provides and other applications. hardware support for securing user software code by preventing unauthorized reading from the internal code. When using this
External Memory
feature, the processor does not boot-load any external code, exe- The external port interface supports access to the external mem- cuting exclusively from internal ROM. Additionally, the ory through core and DMA accesses. The external memory processor is not freely accessible via the JTAG port. Instead, a address space is divided into four banks. Any bank can be pro- unique 64-bit key, which must be scanned in through the JTAG grammed as either asynchronous or synchronous memory. The or Test Access Port will be assigned to each customer. The external ports are comprised of the following modules. device will ignore a wrong key. Emulation features are available after the correct key is scanned. • An Asynchronous Memory Interface which communicates with SRAM, FLASH, and other devices that meet the stan-
On-Chip Memory Bandwidth
dard asynchronous SRAM access protocol. The AMI The internal memory architecture allows programs to have four supports 6M words of external memory in bank 0 and 8M accesses at the same time to any of the four blocks (assuming words of external memory in bank 1, bank 2, and bank 3. there are no block conflicts). The total bandwidth is realized • A SDRAM controller that supports a glueless interface with using the DMD and PMD buses (2 × 64-bits, CCLK speed) and any of the standard SDRAMs. The SDC supports 62M the IOD0/1 buses (2 × 32-bit, PCLK speed). words of external memory in bank 0, and 64M words of external memory in bank 1, bank 2, and bank 3. NOTE: This feature is not available on the ADSP-21486 product. Rev. H | Page 7 of 71 | February 2020 Document Outline Features Table of Contents Revision History General Description Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Timer Data Register File Context Switch Universal Registers Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators With Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Variable Instruction Set Architecture (VISA) On-Chip Memory ROM Based Security On-Chip Memory Bandwidth Family Peripheral Architecture External Memory External Port Asynchronous Memory Controller SDRAM Controller SIMD Access to External Memory VISA and ISA Access to External Memory Pulse-Width Modulation MediaLB Digital Applications Interface (DAI) Serial Ports (SPORTs) S/PDIF-Compatible Digital Audio Receiver/Transmitter Asynchronous Sample Rate Converter (SRC) Input Data Port Precision Clock Generators Digital Peripheral Interface (DPI) Serial Peripheral (Compatible) Interface (SPI) UART Port Timers 2-Wire Interface Port (TWI) I/O Processor Features DMA Controller Delay Line DMA Scatter/Gather DMA FFT Accelerator FIR Accelerator IIR Accelerator Watchdog Timer System Design Program Booting Power Supplies Static Voltage Scaling (SVS) Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings ESD Sensitivity Maximum Power Dissipation Timing Specifications Core Clock Requirements Voltage Controlled Oscillator (VCO) Power-Up Sequencing Clock Input Clock Signals Reset Running Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Watchdog Timer Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags SDRAM Interface Timing (166 MHz SDCLK) AMI Read AMI Write Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port Pulse-Width Modulation Generators (PWM) S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave Media Local Bus Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing 2-Wire Interface (TWI)—Receive and Transmit Timing JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics Thermal Diode 88-Lead LFCSP_VQ Lead Assignment 100-Lead LQFP_EP Lead Assignment 176-Lead LQFP_EP Lead Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide