Datasheet ADSP-21065L-EP (Analog Devices) - 2

ADSP-21065L-EP Enhanced Product FEATURES 60 MIPS, 180 MFLOPS peak, 120 MFLOPS sustained DMA Controller performance Ten DMA channels—two dedicated to the external port and User-configurable 544K bits on-chip SRAM memory eight dedicated to the serial ports Two external port, DMA channels and eight serial port, DMA Background DMA transfers at up to 60 MHz, in parallel with channels full speed processor execution SDRAM controller for glueless interface to low cost external Performs transfers between: memory (@ 60 MHz) Internal RAM and host 64M words external address range Internal RAM and serial ports 12 programmable I/O pins and two timers with event capture Internal RAM and master or slave SHARC options Internal RAM and external memory or I/O devices Code-compatible with ADSP-2106x family External memory and external devices 208-lead MQFP package Matte tin terminal finish Host Processor Interface 3.3 Volt operation Efficient interface to 8-, 16-, and 32-bit microprocessors Host can directly read/write ADSP-21065L-EP IOP registers Flexible Data Formats and 40-Bit Extended Precision 32-bit single-precision and 40-bit extended-precision IEEE Multiprocessing floating-point data formats Distributed on-chip bus arbitration for glueless, parallel 32-bit fixed-point data format, integer and fractional, with bus connect between two ADSP-21065L-EP processors dual 80-bit accumulators plus host 120M bytes/sec transfer rate over parallel bus Parallel Computations Single-cycle multiply and ALU operations in parallel with Serial Ports dual memory read/writes and instruction fetch Independent transmit and receive functions Multiply with add and subtract for accelerated FFT butterfly Programmable 3-bit to 32-bit serial word width computation I2S support allowing eight transmit and eight receive 1024-point complex FFT benchmark: 301 μs (18,221 cycles) channels Glueless interface to industry standard codecs 544K bits Configurable On-Chip SRAM TDM multichannel mode with μ-law/A-law hardware Dual-ported for independent access by core processor and companding DMA Multichannel signaling protocol Configurable in combinations of 16-, 32-, 48-bit data and pro- gram words in Block 0 and Block 1
Rev. B | Page 2 of 14 | September 2017 Document Outline Summary Enhanced Product (EP) Features Features Table of Contents Revision History General Description Pin Function Descriptions Specifications Operating Conditions Absolute Maximum Ratings ESD Caution Package Marking Information Environmental Conditions Thermal Characteristics 208-LEAD MQFP Pin Configuration Outline Dimensions Ordering Guide