Datasheet MCP48CXBXX (Microchip) - 2

MCP48CXBXX General Description
When the VREF pin is used with an external voltage reference, the user can select between a gain of 1 or 2 The MCP48CXBXX are single and dual-channel 8-bit, and can have the reference buffer enabled or disabled. 10-bit, and 12-bit buffered voltage output When the gain is 2, the VREF pin voltage should be Digital-to-Analog Converters (DAC), with volatile or limited to a maximum of VDD/2. MTP memory and an SPI serial interface. These devices have a four-wire SPI-compatible serial The MTP memory can be written by the user up to 32 interface with speeds up to 50 MHz for write and times, for each specific register. It requires a 25 MHz for read operations. high-voltage level on the HVC pin, typically 7.5V, in order to successfully program the desired memory
Applications
location. The nonvolatile memory includes power-up output values, device configuration registers and • Set Point or Offset Trimming general purpose memory. • Sensor Calibration The VREF pin, the device VDD or the internal band gap • Low-Power Portable Instrumentation voltage can be selected as the DAC’s reference • PC Peripherals voltage. When VDD is selected, VDD is internally • Data Acquisition Systems connected to the DAC reference circuit.
MCP48CVBX1 Block Diagram (Single-Channel Output)
VDD
Memory
V Power-up/Brown-out Control SS VOLATILE (4 x 16) SCK DAC0 SPI Serial Interface Module VREF SDI and Control Logic POWER-DOWN (WiperLock™ Technology) SDO GAIN STATUS CS NONVOLATILE (13 x 16) DAC0 VIHH LAT/HVC VREF POWER-DOWN LAT0 GAIN WIPERLOCK™ VDD PD1:PD0 and VREF1:VREF0 Band gap VBG GAIN 1.214V VREF1:VREF0 OPAMP V V OUT0 REF0 VDD r PD1:PD0 sto er k esi 0 R Ladd 1k 10 VREF1:VREF0
Note 1:
Available only on specific packages. DS20006160A-page 2  2019 Microchip Technology Inc. Document Outline 8/10/12-Bit Digital-to-Analog Converters, 1 LSb INL Single/Dual Voltage Outputs with SPI Interface Features Package Types General Description Applications MCP48CVBX1 Block Diagram (Single-Channel Output) MCP48CVBX2 Block Diagram (Dual-Channel Output) Family Device Features 1.0 Electrical Characteristics Absolute Maximum Ratings DC Characteristics DC Notes 1.1 Timing Waveforms and Requirements FIGURE 1-1: VOUT Settling Time Waveforms. TABLE 1-1: Wiper Settling Timing FIGURE 1-2: LAT Pin Waveforms. TABLE 1-2: LAT Pin Timing FIGURE 1-3: Power-on and Brown-out Reset Waveforms. FIGURE 1-4: SPI Power-Down Waveforms. TABLE 1-3: RESET and Power-Down Timing 1.2 SPI Mode Timing Waveforms and Requirements FIGURE 1-5: SPI Timing Waveform (Mode = ‘11’). TABLE 1-4: SPI Requirements (Mode = ‘11’) FIGURE 1-6: SPI Timing Waveform (Mode = 00). TABLE 1-5: SPI Requirements (Mode = 00) Temperature Specifications 2.0 Typical Performance Curves 2.1 Electrical Data FIGURE 2-1: Average Device Supply Current vs. FSCK Frequency, Voltage and Temperature - Active Interface, VRxB:VRxA = ‘00’, (VDD Mode). FIGURE 2-2: Average Device Supply Current vs. FSCK Frequency, Voltage and Temperature - Active Interface, VRxB:VRxA = ‘01’ (Band Gap Mode). FIGURE 2-3: Average Device Supply Current vs. FSCK Frequency, Voltage and Temperature - Active Interface, VRxB:VRxA = ‘11’ (VREF Buffered Mode). FIGURE 2-4: Average Device Supply Current - Inactive Interface (SCK = VIH or VIL) vs. Voltage and Temperature, VRxB:VRxA = ‘00’ (VDD Mode). FIGURE 2-5: Average Device Supply Current - Inactive Interface (SCK = VIH or VIL) vs. Voltage and Temperature, VRxB:VRxA = ‘01’ (Band Gap Mode). FIGURE 2-6: Average Device Supply Current - Inactive Interface (SCK = VIH or VIL) vs. Voltage and Temperature, VRxB:VRxA = ‘11’ (VREF Buffered Mode). FIGURE 2-7: Average Device Supply Current vs. FSCK Frequency, Voltage and Temperature - Active Interface, VRxB:VRxA = ‘10’ (VREF Unbuffered Mode). FIGURE 2-8: Average Device Supply Active Current (IDDA) (at 5.5V and FSCK = 50 MHz) vs. Temperature and DAC Reference Voltage Mode. FIGURE 2-9: Average Device Supply Current - Inactive Interface (SCK = VIH or VIL) vs. Voltage and Temperature, VRxB:VRxA = ‘10’ (VREF Unbuffered Mode). 2.2 Linearity Data FIGURE 2-10: Total Unadjusted Error (VOUT) vs. DAC Code and Temperature (Single-Channel - MCP48CXB21), VDD = 5.5V. FIGURE 2-11: Total Unadjusted Error (VOUT) vs. DAC Code and Temperature (Single-Channel - MCP48CXB21), VDD = 2.7V. FIGURE 2-12: Total Unadjusted Error (VOUT) vs. DAC Code and Temperature (Single-Channel - MCP48CXB21), VDD = 1.8V. FIGURE 2-13: Total Unadjusted Error (VOUT) vs. DAC Code and Temperature (Dual-Channel - MCP48CXB22), VDD = 5.5V. FIGURE 2-14: Total Unadjusted Error (VOUT) vs. DAC Code and Temperature (Dual-Channel - MCP48CXB22), VDD = 2.7V. FIGURE 2-15: Total Unadjusted Error (VOUT) vs. DAC Code and Temperature (Dual-Channel - MCP48CXB22), VDD = 1.8V. FIGURE 2-16: INL Error vs. DAC Code and Temperature (Single-Channel - MCP48CXB21), VDD = 5.5V. FIGURE 2-17: INL Error vs. DAC Code and Temperature (Single-Channel - MCP48CXB21), VDD = 2.7V. FIGURE 2-18: INL Error vs. DAC Code and Temperature (Single-Channel - MCP48CXB21), VDD = 1.8V. FIGURE 2-19: INL Error vs. DAC Code and Temperature (Dual-Channel - MCP48CXB22), VDD = 5.5V. FIGURE 2-20: INL Error vs. DAC Code and Temperature (Dual-Channel - MCP48CXB22), VDD = 2.7V. FIGURE 2-21: INL Error vs. DAC Code and Temperature (Dual-Channel - MCP48CXB22), VDD = 1.8V. FIGURE 2-22: DNL Error vs. DAC Code and Temperature (Single-Channel - MCP48CXB21), VDD = 5.5V. FIGURE 2-23: DNL Error vs. DAC Code and Temperature (Single-Channel - MCP48CXB21), VDD = 2.7V. FIGURE 2-24: DNL Error vs. DAC Code and Temperature (Single-Channel - MCP48CXB21), VDD = 1.8V. FIGURE 2-25: DNL Error vs. DAC Code and Temperature (Dual-Channel - MCP48CXB22), VDD = 5.5V. FIGURE 2-26: DNL Error vs. DAC Code and Temperature (Dual-Channel - MCP48CXB22), VDD = 2.7V. FIGURE 2-27: DNL Error vs. DAC Code and Temperature (Dual-Channel - MCP48CXB22), VDD = 1.8V. FIGURE 2-28: Total Unadjusted Error (VOUT) vs. DAC Code and Temperature (Single-Channel - MCP48CXB21), VREF = 0.5 x VDD = 2.75V, Gain = 2X. FIGURE 2-29: Total Unadjusted Error (VOUT) vs. DAC Code and Temperature (Single-Channel - MCP48CXB21), VREF = 0.5 x VDD = 1.35V, Gain = 2X. FIGURE 2-30: Total Unadjusted Error (VOUT) vs. DAC Code, and Temperature (Dual-Channel - MCP48CXB22), VREF = 0.5 x VDD = 2.75V, Gain = 2X. FIGURE 2-31: Total Unadjusted Error (VOUT) vs. DAC Code and Temperature (Dual-Channel - MCP48CXB22), VREF = 0.5 x VDD = 1.35V, Gain = 2X. FIGURE 2-32: INL Error vs. DAC Code and Temperature (Single-Channel - MCP48CXB21), VREF = 0.5 x VDD = 2.75V, Gain = 2X. FIGURE 2-33: INL Error vs. DAC Code and Temperature (Single-Channel - MCP48CXB21), VREF = 0.5 x VDD = 1.35V, Gain = 2X. FIGURE 2-34: INL Error vs. DAC Code and Temperature (Dual-Channel - MCP48CXB22), VREF = 0.5 x VDD = 2.75V, Gain = 2X. FIGURE 2-35: INL Error vs. DAC Code and Temperature (Dual-Channel - MCP48CXB22), VREF = 0.5 x VDD = 1.35V, Gain = 2X. FIGURE 2-36: DNL Error vs. DAC Code and Temperature (Single-Channel - MCP48CXB21), VDD = 5.5V, VREF = 0.5 x VDD = 2.75V. FIGURE 2-37: DNL Error vs. DAC Code and Temperature (Single-Channel - MCP48CXB21), VDD = 5.5V, VREF = 0.5 x VDD = 1.35V. FIGURE 2-38: DNL Error vs. DAC Code and Temperature (Dual-Channel - MCP48CXB22), VDD = 5.5V, VREF = 0.5 x VDD = 2.75V. FIGURE 2-39: DNL Error vs. DAC Code and Temperature (Dual-Channel - MCP48CXB22), VDD = 5.5V, VREF = 0.5 x VDD = 1.35V. FIGURE 2-40: Total Unadjusted Error (VOUT) vs. DAC Code and Temperature (Single-Channel - MCP48CXB21), VDD = 5.5V, Gain = 1X. FIGURE 2-41: Total Unadjusted Error (VOUT) vs. DAC Code and Temperature (Single-Channel - MCP48CXB21), VDD = 5.5V, Gain = 2X. FIGURE 2-42: Total Unadjusted Error (VOUT) vs. DAC Code and Temperature (Single-Channel - MCP48CXB21), VDD = 2.7V, Gain = 1X. FIGURE 2-43: Total Unadjusted Error (VOUT) vs. DAC Code and Temperature (Dual-Channel - MCP48CXB22), VDD = 5.5V, Gain = 1X. FIGURE 2-44: Total Unadjusted Error (VOUT) vs. DAC Code and Temperature (Dual-Channel - MCP48CXB22), VDD = 5.5V, Gain = 2X. FIGURE 2-45: Total Unadjusted Error (VOUT) vs. DAC Code and Temperature (Dual-Channel - MCP48CXB22), VDD = 2.7V, Gain = 1X. FIGURE 2-46: Total Unadjusted Error (VOUT) vs. DAC Code and Temperature (Single-Channel - MCP48CXB21), VDD = 2.7V, Gain = 2X. FIGURE 2-47: Total Unadjusted Error (VOUT) vs. DAC Code and Temperature (Single-Channel - MCP48CXB21), VDD = 1.8V, Gain = 1X. FIGURE 2-48: Total Unadjusted Error (VOUT) vs. DAC Code, +25°C, Gain = 1X. FIGURE 2-49: Total Unadjusted Error (VOUT) vs. DAC Code and Temperature (Dual-Channel - MCP48CXB22), VDD = 2.7V, Gain = 2X. FIGURE 2-50: Total Unadjusted Error (VOUT) vs. DAC Code and Temperature (Dual-Channel - MCP48CXB22), VDD = 1.8V, Gain = 1X. FIGURE 2-51: Total Unadjusted Error (VOUT) vs. DAC Code, +25°C, Gain = 2X. FIGURE 2-52: Total Unadjusted Error (VOUT) vs. DAC Code, +25°C, Gain = 1X and 2X. FIGURE 2-53: INL Error vs. DAC Code and Temperature (Single-Channel - MCP48CXB21), VDD = 5.5V, Gain = 1X. FIGURE 2-54: INL Error vs. DAC Code and Temperature (Single-Channel - MCP48CXB21), VDD = 5.5V, Gain = 2X. FIGURE 2-55: INL Error vs. DAC Code and Temperature (Single-Channel - MCP48CXB21), VDD = 2.7V, Gain = 1X. FIGURE 2-56: INL Error vs. DAC Code and Temperature (Dual-Channel - MCP48CXB22), VDD = 5.5V, Gain = 1X. FIGURE 2-57: INL Error vs. DAC Code and Temperature (Dual-Channel - MCP48CXB22), VDD = 5.5V, Gain = 2X. FIGURE 2-58: INL Error vs. DAC Code and Temperature (Dual-Channel - MCP48CXB22), VDD = 2.7V, Gain = 1X. FIGURE 2-59: INL Error vs. DAC Code and Temperature (Single-Channel - MCP48CXB21), VDD = 2.7V, Gain = 2X. FIGURE 2-60: INL Error vs. DAC Code and Temperature (Single-Channel - MCP48CXB21), VDD = 1.8V, Gain = 1X. FIGURE 2-61: INL Error vs. DAC Code, +25°C, Gain = 1X. FIGURE 2-62: INL Error vs. DAC Code and Temperature (Dual-Channel - MCP48CXB22), VDD = 2.7V, Gain = 2X. FIGURE 2-63: INL Error vs. DAC Code and Temperature (Dual-Channel - MCP48CXB22), VDD = 1.8V, Gain = 1X. FIGURE 2-64: INL Error vs. DAC Code, +25°C, Gain = 2X. FIGURE 2-65: INL Error vs. DAC Code, +25°C, Gain = 1X and 2X. FIGURE 2-66: DNL Error vs. DAC Code and Temperature (Single-Channel - MCP48CXB21), VDD = 5.5V, Gain = 1X. FIGURE 2-67: DNL Error vs. DAC Code and Temperature (Single-Channel - MCP48CXB21), VDD = 5.5V, Gain = 2X. FIGURE 2-68: DNL Error vs. DAC Code and Temperature (Single-Channel - MCP48CXB21), VDD = 2.7V, Gain = 1X. FIGURE 2-69: DNL Error vs. DAC Code and Temperature (Dual-Channel - MCP48CXB22), VDD = 5.5V, Gain = 1X. FIGURE 2-70: DNL Error vs. DAC Code and Temperature (Dual-Channel - MCP48CXB22), VDD = 5.5V, Gain = 2X. FIGURE 2-71: DNL Error vs. DAC Code and Temperature (Dual-Channel - MCP48CXB22), VDD = 2.7V, Gain = 1X. FIGURE 2-72: DNL Error vs. DAC Code and Temperature (Single-Channel - MCP48CXB21), VDD = 2.7V, Gain = 2X. FIGURE 2-73: DNL Error vs. DAC Code and Temperature (Single-Channel - MCP48CXB21), VDD = 1.8V, Gain = 1X. FIGURE 2-74: DNL Error vs. DAC Code, +25°C, Gain = 1X. FIGURE 2-75: DNL Error vs. DAC Code and Temperature (Dual-Channel - MCP48CXB22), VDD = 2.7V, Gain = 2X. FIGURE 2-76: DNL Error vs. DAC Code and Temperature (Dual-Channel - MCP48CXB22), VDD = 1.8V, Gain = 1X. FIGURE 2-77: DNL Error vs. DAC Code, +25°C, Gain = 2X. FIGURE 2-78: DNL Error vs. DAC Code, +25°C, Gain = 1X and 2X. 3.0 Pin Descriptions TABLE 3-1: MCP48CXBX1 (Single-DAC) Pin Function Table TABLE 3-2: MCP48CXBX2 (Dual-DAC) Pin Function Table 3.1 Positive Power Supply Input (VDD) 3.2 Ground (VSS) 3.3 Voltage Reference Pin (VREF) 3.4 No Connect (NC) 3.5 Analog Output Voltage Pins (VOUT0, VOUT1) 3.6 Latch/High-Voltage Command Pin (LAT/HVC) 3.7 SPI - Chip Select Pin (CS) 3.8 SPI - Serial Clock Pin (SCK) 3.9 SPI - Serial Data In Pin (SDI) 3.10 SPI - Serial Data Out Pin (SDO) 4.0 General Description 4.1 Power-on Reset/Brown-out Reset (POR/BOR) FIGURE 4-1: Power-on Reset Operation. 4.2 Device Memory TABLE 4-1: MCP48CXBXX MEMORY MAP (16-bit) TABLE 4-2: Factory Default POR/BOR Values (MTP Memory Unprogrammed) Register 4-1: DAC0 (00h/10h) and DAC1 (01h/11h) OUTPUT VALUE Registers (Volatile/NONvOLATILE) Register 4-2: Voltage Reference (VREF) Control Registers (08h/18h) (Volatile/NONVOLATILE) Register 4-3: Power-down Control Registers (09h/19h) (VOLATILE/NONVOLATILE) Register 4-4: Gain Control and System Status Register (0Ah) (VOLATILE) Register 4-5: Gain Control Register (1AH) (Nonvolatile) Register 4-6: WiperLock Technology Control Register (1Bh) (NonVolatile) 5.0 DAC Circuitry FIGURE 5-1: MCP48CXBXX DAC Module Block Diagram. 5.1 Resistor Ladder FIGURE 5-2: Resistor Ladder Model Block Diagram. 5.2 Voltage Reference Selection FIGURE 5-3: Resistor Ladder Reference Voltage Selection Block Diagram. FIGURE 5-4: Reference Voltage Selection Implementation Block Diagram. TABLE 5-1: VOUT Using Band Gap 5.3 Output Buffer/VOUT Operation FIGURE 5-5: Output Driver Block Diagram. TABLE 5-2: Output Driver Gain FIGURE 5-6: VOUT Pin Slew Rate. FIGURE 5-7: Circuit to Stabilize Output Buffer for Large Capacitive Loads (CL). TABLE 5-3: Theoretical Step Voltage (VS)(1) 5.4 Latch Pin (LAT) FIGURE 5-8: LAT and DAC Interaction. FIGURE 5-9: Example Use of LAT Pin Operation. 5.5 Power-Down Operation TABLE 5-4: Power-Down Bits and Output Resistive Load TABLE 5-5: DAC Current Sources TABLE 5-6: DAC Input Code Vs. Calculated Analog Output (VOUT) (VDD = 5.0V) 6.0 SPI Serial Interface Module FIGURE 6-1: Typical SPI Interface. 6.1 Overview 6.2 Communication Data Rates 6.3 POR/BOR 6.4 Interface Pins (CS, SCK, SDI, SDO, and LAT/HVC) TABLE 6-1: SCK Frequency 6.5 Device Memory Address 6.6 SPI Modes FIGURE 6-2: 24-Bit Commands (Write, Read) - SPI Waveform (Mode 0,0). FIGURE 6-3: 24-Bit Commands (Write, Read) - SPI Waveform (Mode 1,1). 7.0 Device Commands TABLE 7-1: COMMAND BITS OVERVIEW FIGURE 7-1: 24-bit SPI Command Format. TABLE 7-2: SPI Commands - Number of Clocks 7.1 Command Byte 7.2 Data Bytes 7.3 Error Condition 7.4 Continuous Commands 7.5 Write Command FIGURE 7-2: Write Single Memory Location Command - SDI and SDO States. FIGURE 7-3: Continuous Write Sequence (Volatile Memory Only). 7.6 Read Command FIGURE 7-4: Read Single Memory Location Command - SDI and SDO States. FIGURE 7-5: Continuous Read Sequence. 8.0 Typical Applications 8.1 Design Considerations FIGURE 8-1: Example Circuit. TABLE 8-1: Package Footprint(1) 8.2 Application Examples FIGURE 8-2: Example Circuit Of Set Point or Threshold Calibration. FIGURE 8-3: Single-Supply “Window” DAC. 8.3 Bipolar Operation FIGURE 8-4: Digitally-Controlled Bipolar Voltage Source Example Circuit. 8.4 Selectable Gain and Offset Bipolar Voltage Output FIGURE 8-5: Bipolar Voltage Source with Selectable Gain and Offset. 8.5 Designing a Double-Precision DAC FIGURE 8-6: Simple Double Precision DAC Using MCP48CVBX2. 8.6 Building Programmable Current Source FIGURE 8-7: Digitally-Controlled Current Source. 8.7 Serial Interface Communication Times 9.0 Development Support 9.1 Development Tools 9.2 Technical Documentation TABLE 9-1: Development Tools (Note 1) TABLE 9-2: Technical Documentation FIGURE 9-1: MCP48CXBXX Evaluation Board Circuit Using ADM00309. 10.0 Packaging Information 10.1 Package Marking Information Appendix A: Revision History Revision A (February 2019) Appendix B: Terminology B.1 Resolution B.2 Least Significant Bit (LSb) B.3 Monotonic Operation B.4 Full-Scale Error (EFS) B.5 Zero-Scale Error (EZS) B.6 Total Unadjusted Error (ET) B.7 Offset Error (EOS) B.8 Offset Error Drift (EOSD) B.9 Gain Error (EG) B.10 Gain Error Drift (EGD) B.11 Integral Nonlinearity (INL) B.12 Differential Nonlinearity (DNL) B.13 Settling Time B.14 Major-Code Transition Glitch B.15 Digital Feed-Through B.16 -3 dB Bandwidth B.17 Power-Supply Sensitivity (PSS) B.18 Power-Supply Rejection Ratio (PSRR) B.19 VOUT Temperature Coefficient B.20 Absolute Temperature Coefficient B.21 Noise Spectral Density Product Identification System Trademarks Worldwide Sales and Service