Datasheet ISL9122A (Renesas) - 8

link to page 8 link to page 8 ISL9122A 2. Specifications
2.5 I2C Interface Timing Specifications
Applicable to SCL and SDA in the Fast mode I2C operation, unless otherwise specified.
Min Max Parameter Symbol Test Conditions (Note 6) Typ (Note 6 ) Unit
I2C Frequency Capability fI2C 0 400 kHz Pulse Width Suppression Time at SDA tSP Any pulse narrower than the maximum specification 50 ns and SCL Inputs is suppressed Data Valid Time tVD;DAT Time from SCL falling edge crossing SCLIL to SDA 900 ns exiting the SDAIL to SDAIH window Data Valid Acknowledge Time tVD;ACK Time from SCL falling edge crossing SCLIL to SDA 900 ns exiting the SDAIL to SDAIH window, during acknowledgment Bus Free Time Between a STOP and tBUF Time from SDA crossing SDAIH at STOP to SDA 1300 ns START Condition crossing SDAIH at the following START SCL Low Time tLOW Measured at the SCLIL crossing 1300 ns SCL High Time tHIGH Measured at the SCLIH crossing 600 ns START Condition Set-Up Time tSU;STA Time from SCL rising edge crossing SCLIH to SDA 600 ns falling edge crossing SDAIH START Condition Hold Time tHD;STA Time from SDA falling edge crossing SDAIL to SCL 600 ns falling edge crossing SCLIH Data Set-Up Time tSU;DAT Time from SDA exiting the SDAIL to SDAIH window 100 ns to SCL rising edge crossing SCLIL Data Hold Time tHD;DAT Time from SCL falling edge crossing SCLIL to SDA 50 ns entering the SDAIL to SDAIH window STOP Condition Set-Up Time tSU;STO Time from SCL rising edge crossing SCLIH to SDA 600 ns rising edge crossing SDAIL SCL/SDA Capacitive Loading Cb Capacitive load for each bus line 400 pF
Note:
6. Limits established by design and are not production tested. FN8947 Rev.1.00 Page 8 of 20 Sep.14.20 Document Outline Features Applications Related Literature Contents 1. Overview 1.1 Block Diagram 1.2 Ordering Information 1.3 Pin Configurations 1.4 Pin Descriptions 2. Specifications 2.1 Absolute Maximum Ratings 2.2 Thermal Information 2.3 Recommended Operation Conditions 2.4 Analog Specifications 2.5 I2C Interface Timing Specifications 3. Typical Performance Curves 4. Functional Description 4.1 Enable Input 4.2 Soft Discharge 4.3 Start-Up 4.4 Overcurrent/Short-Circuit Protection 4.5 Thermal Shutdown 4.6 Buck-Boost Conversion Topology 4.7 PWM Operation 4.8 PFM Operation 4.9 Operation With VIN Close to VOUT 4.10 Forced Operating Modes 4.11 I2C Serial Interface 4.12 Protocol Conventions 4.13 Write Operation 4.14 Read Operation 4.15 Register Descriptions 4.15.1 RO_REG1 4.15.2 INTFLG_REG 4.15.3 VSET 4.15.4 CONV_CFG 4.15.5 INTFLG_MASK 5. Revision History 6. Package Outline Drawings