Datasheet AD8099 (Analog Devices) - 5
| 制造商 | Analog Devices |
| 描述 | Ultralow Distortion, High Speed 0.95nV/√Hz Voltage Noise Op Amp |
| 页数 / 页 | 26 / 5 — Data Sheet. AD8099. ABSOLUTE MAXIMUM RATINGS. Table 3. Parameter. Rating. … |
| 修订版 | E |
| 文件格式/大小 | PDF / 581 Kb |
| 文件语言 | 英语 |
Data Sheet. AD8099. ABSOLUTE MAXIMUM RATINGS. Table 3. Parameter. Rating. MAXIMUM POWER DISSIPATION. 4.0. 3.5. 3.0. 2.5. 2.0. 1.5. LFCSP AND SOIC
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Data Sheet AD8099 ABSOLUTE MAXIMUM RATINGS
2
Table 3.
P = (V × I ) V V V S OUT OUT + × – D S S
Parameter Rating
2 R R L L Supply Voltage 12.6 V RMS output voltages should be considered. If RL is referenced to Power Dissipation See Figure 4 VS−, as in single-supply operation, then the total drive power is Differential Input Voltage ±1.8 V VS × IOUT. If the rms signal levels are indeterminate, consider the Differential Input Current ±10mA worst case, when VOUT = VS/4 for RL to midsupply: Storage Temperature Range −65°C to +125°C V / 2 4 Operating Temperature Range −40°C to +125°C P = (V × I ) ( ) S + D S S Lead Temperature (Soldering 10 sec) 300°C RL Junction Temperature 150°C In single-supply operation with RL referenced to VS–, worst case Stresses at or above those listed under Absolute Maximum is VOUT = VS/2. Ratings may cause permanent damage to the product. This is a Airflow increases heat dissipation, effectively reducing θJA. Also, stress rating only; functional operation of the product at these more metal directly in contact with the package leads from metal or any other conditions above those indicated in the operational traces, through holes, ground, and power planes reduce the θJA. section of this specification is not implied. Operation beyond Soldering the exposed paddle to the ground plane significantly the maximum operating conditions for extended periods may reduces the overal thermal resistance of the package. Take care affect product reliability. to minimize parasitic capacitances at the input leads of high
MAXIMUM POWER DISSIPATION
speed op amps, as discussed in the PCB Layout section. The maximum safe power dissipation in the AD8099 package is Figure 4 shows the maximum safe power dissipation in the limited by the associated rise in junction temperature (T package versus the ambient temperature for the exposed paddle J) on the die. The plastic encapsulating the die locally reaches the (EPAD) SOIC-8 (70°C/W), and LFCSP (70°C/W), packages on junction temperature. At approximately 150°C, which is the a JEDEC standard 4-layer board. θJA values are approximations. glass transition temperature, the plastic changes its properties.
4.0
Even temporarily exceeding this temperature limit may change
3.5
the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8099. Exceeding
3.0
a junction temperature of 150°C for an extended period can
2.5
result in changes in silicon devices, potentially causing failure.
2.0
The still-air thermal properties of the package and PCB (θJA), the ambient temperature (T
1.5
A), and the total power dissipated in
LFCSP AND SOIC
the package (PD) determine the junction temperature of the die.
1.0
The junction temperature can be calculated as
0.5
T = T + P × θ
MAXIMUM POWER DISSIPATION (Watts)
J A ( D JA)
0.0
The power dissipated in the package (P
–40 –20 0 20 40 60 80 100 120
D) is the sum of the
AMBIENT TEMPERATURE (°C)
quiescent power dissipation and the power dissipated in the 04511-0-115 package due to the load drive for al outputs. The quiescent Figure 4. Maximum Power Dissipation power is the voltage between the supply pins (VS) times the
ESD CAUTION
quiescent current (IS). Assuming the load (RL) is referenced to midsupply, the total drive power is VS/2 × IOUT, some of which is dissipated in the package and some in the load (VOUT × IOUT). The difference between the total drive power and the load power is the drive power dissipated in the package. PD = Quiescent Power + (Total Drive Power − Load Power) Rev. E | Page 5 of 26 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION CONNECTION DIAGRAMS REVISION HISTORY SPECIFICATIONS SPECIFICATIONS WITH ±5 V SUPPLY SPECIFICATIONS WITH +5 V SUPPLY ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION ESD CAUTION TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION USING THE AD8099 CIRCUIT COMPONENTS RECOMMENDED VALUES CIRCUIT CONFIGURATIONS PERFORMANCE vs. COMPONENT VALUES TOTAL OUTPUT NOISE CALCULATIONS AND DESIGN INPUT BIAS CURRENT AND DC OFFSET PIN AND INPUT BIAS CANCELLATION 16-BIT ADC DRIVER CIRCUIT CONSIDERATIONS PCB Layout Parasitics Grounding Power Supply Bypassing Component Selection DESIGN TOOLS AND TECHNICAL SUPPORT OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet AD8099 ABSOLUTE MAXIMUM RATINGS
2
Table 3.
P = (V × I ) V V V S OUT OUT + × – D S S
Parameter Rating
2 R R L L Supply Voltage 12.6 V RMS output voltages should be considered. If RL is referenced to Power Dissipation See Figure 4 VS−, as in single-supply operation, then the total drive power is Differential Input Voltage ±1.8 V VS × IOUT. If the rms signal levels are indeterminate, consider the Differential Input Current ±10mA worst case, when VOUT = VS/4 for RL to midsupply: Storage Temperature Range −65°C to +125°C V / 2 4 Operating Temperature Range −40°C to +125°C P = (V × I ) ( ) S + D S S Lead Temperature (Soldering 10 sec) 300°C RL Junction Temperature 150°C In single-supply operation with RL referenced to VS–, worst case Stresses at or above those listed under Absolute Maximum is VOUT = VS/2. Ratings may cause permanent damage to the product. This is a Airflow increases heat dissipation, effectively reducing θJA. Also, stress rating only; functional operation of the product at these more metal directly in contact with the package leads from metal or any other conditions above those indicated in the operational traces, through holes, ground, and power planes reduce the θJA. section of this specification is not implied. Operation beyond Soldering the exposed paddle to the ground plane significantly the maximum operating conditions for extended periods may reduces the overal thermal resistance of the package. Take care affect product reliability. to minimize parasitic capacitances at the input leads of high
MAXIMUM POWER DISSIPATION
speed op amps, as discussed in the PCB Layout section. The maximum safe power dissipation in the AD8099 package is Figure 4 shows the maximum safe power dissipation in the limited by the associated rise in junction temperature (T package versus the ambient temperature for the exposed paddle J) on the die. The plastic encapsulating the die locally reaches the (EPAD) SOIC-8 (70°C/W), and LFCSP (70°C/W), packages on junction temperature. At approximately 150°C, which is the a JEDEC standard 4-layer board. θJA values are approximations. glass transition temperature, the plastic changes its properties.
4.0
Even temporarily exceeding this temperature limit may change
3.5
the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8099. Exceeding
3.0
a junction temperature of 150°C for an extended period can
2.5
result in changes in silicon devices, potentially causing failure.
2.0
The still-air thermal properties of the package and PCB (θJA), the ambient temperature (T
1.5
A), and the total power dissipated in
LFCSP AND SOIC
the package (PD) determine the junction temperature of the die.
1.0
The junction temperature can be calculated as
0.5
T = T + P × θ
MAXIMUM POWER DISSIPATION (Watts)
J A ( D JA)
0.0
The power dissipated in the package (P
–40 –20 0 20 40 60 80 100 120
D) is the sum of the
AMBIENT TEMPERATURE (°C)
quiescent power dissipation and the power dissipated in the 04511-0-115 package due to the load drive for al outputs. The quiescent Figure 4. Maximum Power Dissipation power is the voltage between the supply pins (VS) times the
ESD CAUTION
quiescent current (IS). Assuming the load (RL) is referenced to midsupply, the total drive power is VS/2 × IOUT, some of which is dissipated in the package and some in the load (VOUT × IOUT). The difference between the total drive power and the load power is the drive power dissipated in the package. PD = Quiescent Power + (Total Drive Power − Load Power) Rev. E | Page 5 of 26 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION CONNECTION DIAGRAMS REVISION HISTORY SPECIFICATIONS SPECIFICATIONS WITH ±5 V SUPPLY SPECIFICATIONS WITH +5 V SUPPLY ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION ESD CAUTION TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION USING THE AD8099 CIRCUIT COMPONENTS RECOMMENDED VALUES CIRCUIT CONFIGURATIONS PERFORMANCE vs. COMPONENT VALUES TOTAL OUTPUT NOISE CALCULATIONS AND DESIGN INPUT BIAS CURRENT AND DC OFFSET PIN AND INPUT BIAS CANCELLATION 16-BIT ADC DRIVER CIRCUIT CONSIDERATIONS PCB Layout Parasitics Grounding Power Supply Bypassing Component Selection DESIGN TOOLS AND TECHNICAL SUPPORT OUTLINE DIMENSIONS ORDERING GUIDE