Datasheet AD8018 (Analog Devices) - 10

AD8018
This circuit requires significant power supply bypassing. The 1 AD8018 operates on a split supply in this circuit. The bypassing P = 4 0 8 2 ( . – ) × + 2 α + TOT VO rmsVS VO rms IQ VS POUT technique shown in TPC 13 utilizes a 220 µF tantalum capacitor RL and a 0.1 µF ceramic chip capacitor in parallel, connected from For the AD8018, operating on a single 5 V supply and deliver- the positive to negative supply, and a 10 µF tantalum and 0.1 µF ing a total of 16 dBm (13 dBm to the line and 3 dBm to the ceramic chip capacitor in parallel, connected from each supply to matching network) into 12.5 Ω (100 Ω reflected back through ground. The capacitors connected between the power supplies a 1:4.0 transformer plus back termination), the power is: serve to minimize any voltage ripples that might appear at the = 261 mW + 40 mW supplies while sourcing or sinking any large differential current. The large capacitor has a pool of charge instantly available for = 301 mW the AD8018 to draw from, thus preventing any erroneous dis- Using these calculations, and a θJA of 115°C/W for the TSSOP tortion results. package and 100°C/W for the SOIC, Tables III and IV show junction temperature versus power delivered to the line for sev-
POWER DISSIPATION
eral supply voltages. It is important to consider the total power dissipation of the AD8018 in order to properly size the heat sink area of an
Table III. Junction Temperature vs. Line Power and
application. Figure 8 is a simple representation of a differential
Operating Voltage for TSSOP, TAMB = 85
ⴗ
C
driver. With some simplifying assumptions we can estimate the total power dissipated in this circuit. If the output current is
VSUPPLY
large compared to the quiescent current, computing the dissipa-
PLINE, dBm 5 6 7 8
tion in the output devices and adding it to the quiescent power 13 115 122 129 136 dissipation will give a close approximation of the total power 14 117 125 132 140 dissipation in the package. A factor α (~0.6-1) corrects for the 15 119 127 136 144 slight error due to the Class A/B operation of the output stage. 16 121 130 139 148 It can be estimated by subtracting the quiescent current in the 17 123 133 143 153 output stage from the total quiescent current and ratioing that 18 125 136 147 158 to the total quiescent current. For the AD8018, α = 0.833.
+VS +VS Table IV. Junction Temperature vs. Line Power and Operating Voltage for SOIC, TAMB = 85
ⴗ
C +VO –VO VSUPPLY R P L LINE, dBm 5 6 7 8
13 111 117 123 129 14 113 119 126 133 15 115 122 129 136 16 116 124 132 140
–V –V S S
17 118 127 136 144 18 120 130 139 149 Figure 8. Simplified Differential Driver Remembering that each output device dissipates for only half Running the AD8018 at voltages near 8 V can produce junction the time gives a simple integral that computes the power for temperatures that exceed the thermal rating of the TSSOP pack- each device: ages and should be avoided. The shaded areas indicate junction temperatures greater than 150°C. 1  2VO  ∫ (VS –VO)×   2  RL 
LAYOUT CONSIDERATIONS
As is the case with all high-speed applications, careful attention The total supply power can then be computed as: to printed circuit board layout details will prevent associated board parasitics from becoming problematic. Proper RF design  2  1 P = α TOT 4 VS V ∫| | − O V ∫ O 2 IQ VS POUT technique is mandatory. The PCB should have a ground plane   × + + RL covering all unused portions of the component side of the board In this differential driver, V to provide a low-impedance return path. Removing the ground O is the voltage at the output of one amplifier, so 2 V plane on all layers from the area near the input and output pins O is the voltage across RL, which is the total impedance seen by the differential driver, including back termina- will reduce stray capacitance, particularly in the area of the tion. Now, with two observations, the integrals are easily evaluated. inverting inputs. Signal lines connecting the feedback and gain First, the integral of V 2 is simply the square of the rms value of resistors should be as short as possible to minimize the inductance O V and stray capacitance associated with these traces. Termination O. Second, the integral of |VO| is equal to the average recti- fied value of V resistors and loads should be located as close as possible to their O, sometimes called the Mean Average Deviation, or MAD. It can be shown that for a Discrete MultiTone (DMT) respective inputs and outputs. Input and output traces should signal, the MAD value is equal to 0.8 times the rms value. be kept as far apart as possible to minimize coupling (crosstalk) though the board. Adherence to stripline design techniques for long signal traces (greater than about 1 inch) is recommended. –10– REV. A